NXP Semiconductors K22F series, Reference Manual, Page: 155 / 1407

Table 5-1. Clock Summary (continued)
Clock name High Speed Run
mode
clock frequency
Run mode
clock frequency
VLPR mode
clock frequency
Clock source Clock is disabled
when…
External reference
32kHz
(ERCLK32K)
30-40 kHz 30-40 kHz 30-40 kHz System OSC or
LPO or RTC OSC
depending on
SIM_SOPT1[OSC3
2KSEL] System OSC's
OSC_CR[ERCLKE
N] cleared
or RTC's
RTC_CR[OSCE]
cleared
Internal 48 MHz
clock
(IRC48MCLK)
48 MHz 48 MHz N/A IRC48M USB MCG or SIM
control does not
enable.
Overriding forced
disable in VLPS,
LLSx, VLLSx.
RTC_CLKOUT 1 Hz or 32 kHz 1 Hz or 32 kHz 1 Hz or 32 kHz RTC clock RTC_CLKOUT is
disabled in LLS and
VLLSx modes.
Overriding clocking
is possible via
SIM_SOPT1[OSC3
2KOUT] to drive
CLKOUT32K out in
all low power
modes.
CLKOUT32K 32 kHz 32 kHz 32 kHz ERCLK32K - which
is system OSC or
LPO or RTC OSC
depending on
SIM_SOPT1[OSC3
2KSEL] SIM_SOPT1[OSC3
2KOUT] not
configured to drive
ERCLK32K out.
LPO 1 kHz 1 kHz 1 kHz PMC in VLLS0
USB FS clock 48 MHz 48 MHz N/A IRC48MCLK
orMCGPLLCLK or
MCGFLLCLK with
fractional clock
divider, or
USB_CLKIN
USB FS OTG is
disabled
I2S master clock Up to 25 MHz Up to 25 MHz Up to 12.5 MHz System clock ,
MCGPLLCLK,
IRC48MCLK,
OSCERCLK with
fractional clock
divider, or
I2S_CLKIN
I
2
S is disabled
TRACE clock Up to 120 MHz Up to 120 MHz Up to 4 MHz System clock or
MCGOUTCLK
Trace is disabled
LPUART0 clock Up to 100 MHz Up to 100MHz Up to 16MHz MCGFLLCLK or
IRC48MCLK or
LPUART0 is
disabled
Chapter 5 Clock Distribution
K22F Sub-Family Reference Manual, Rev. 4, 08/2016
NXP Semiconductors 155