NXP Semiconductors K22F series, Reference Manual, Page: 560 / 1407

Table 25-3. MCG modes of operation (continued)
Mode Description
• 0 is written to C1[IREFS].
• 1 is written to C6[PLLS].
• 0 is written to C2[LP].
In PBE mode, MCGOUTCLK is derived from the OSCSEL external reference clock; the PLL is
operational, but its output clock is not used. This mode is useful to allow the PLL to acquire its target
frequency while MCGOUTCLK is driven from the external reference clock. The PLL clock frequency
locks to a multiplication factor, as specified by its [VDIV], times the PLL reference frequency, as
specified by its [PRDIV]. In preparation for transition to PEE, the PLL's programmable reference
divider must be configured to produce a valid PLL reference clock. The FLL is disabled in a low-
power state.
Bypassed Low Power
Internal (BLPI)
1
Bypassed Low Power Internal (BLPI) mode is entered when all the following conditions occur:
• 01 is written to C1[CLKS].
• 1 is written to C1[IREFS].
• 0 is written to C6[PLLS].
• 1 is written to C2[LP].
In BLPI mode, MCGOUTCLK is derived from the internal reference clock. The FLL is disabled and
PLL is disabled even if C5[PLLCLKEN] is set to 1.
Bypassed Low Power
External (BLPE)
1
Bypassed Low Power External (BLPE) mode is entered when all the following conditions occur:
• 10 is written to C1[CLKS].
• 0 is written to C1[IREFS].
• 1 is written to C2[LP].
In BLPE mode, MCGOUTCLK is derived from the OSCSEL external reference clock. The FLL is
disabled and PLL is disabled even if the C5[PLLCLKEN] is set to 1.
Stop Entered whenever the MCU enters a Stop state. The power modes are chip specific. For power
mode assignments, see the chapter that describes how modules are configured and MCG behavior
during Stop recovery. Entering Stop mode, the FLL is disabled, and all MCG clock signals are static
except in the following case:
MCGPLLCLK is active in Normal Stop mode when PLLSTEN=1
MCGIRCLK is active in Normal Stop mode when all the following conditions become true:
• C1[IRCLKEN] = 1
• C1[IREFSTEN] = 1
NOTE:
• When entering Low Power Stop modes (LLS or VLPS) from PEE mode, on exit the
MCG clock mode is forced to PBE clock mode. C1[CLKS] and S[CLKST] will be
configured to 2’b10 and S[LOCK] bit will be cleared without setting S[LOLS].
• When entering Normal Stop mode from PEE mode and if C5[PLLSTEN]=0, on exit
the MCG clock mode is forced to PBE mode, the C1[CLKS] and S[CLKST] will be
configured to 2’b10 and S[LOCK] bit will clear without setting S[LOLS]. If
C5[PLLSTEN]=1, the S[LOCK] bit will not get cleared and on exit the MCG will
continue to run in PEE mode.
Functional description
K22F Sub-Family Reference Manual, Rev. 4, 08/2016
560 NXP Semiconductors