NXP Semiconductors K22F series, Reference Manual, Page: 1360 / 1407

49.3.15 SAI Receive Configuration 5 Register (I2Sx_RCR5)
This register must not be altered when RCSR[RE] is set.
Address: 4002_F000h base + 94h offset = 4002_F094h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
0
WNW
0
W0W
0
FBT
0
W
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
I2Sx_RCR5 field descriptions
Field Description
31–29
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
28–24
WNW
Word N Width
Configures the number of bits in each word, for each word except the first in the frame. The value written
must be one less than the number of bits per word. Word width of less than 8 bits is not supported.
23–21
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
20–16
W0W
Word 0 Width
Configures the number of bits in the first word in each frame. The value written must be one less than the
number of bits in the first word. Word width of less than 8 bits is not supported if there is only one word per
frame.
15–13
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
12–8
FBT
First Bit Shifted
Configures the bit index for the first bit received for each word in the frame. If configured for MSB First, the
index of the next bit received is one less than the current bit received. If configured for LSB First, the index
of the next bit received is one more than the current bit received. The value written must be greater than or
equal to the word width when configured for MSB First. The value written must be less than or equal to 31-
word width when configured for LSB First.
Reserved This field is reserved.
This read-only field is reserved and always has the value 0.
49.3.16 SAI Receive Data Register (I2Sx_RDRn)
Reading this register introduces one additional peripheral clock wait state on each read.
Address: 4002_F000h base + A0h (4d × i), where i=0d to 0d
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
RDR
W
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Memory map and register definition
K22F Sub-Family Reference Manual, Rev. 4, 08/2016
1360 NXP Semiconductors