NXP Semiconductors K22F series, Reference Manual, Page: 1226 / 1407

UARTx_BDL field descriptions (continued)
Field Description
• Writing to BDH has no effect without writing to BDL, because writing to BDH puts the data
in a temporary location until BDL is written.
• When the 1/32 narrow pulse width is selected for infrared (IrDA), the baud rate fields must
be even, the least significant bit is 0. See MODEM register for more details.
47.3.3 UART Control Register 1 (UARTx_C1)
This read/write register controls various optional features of the UART system.
Address: Base a 2h offset
Bit 7 6 5 4 3 2 1 0
Read
LOOPS UARTSWAI RSRC M WAKE ILT PE PT
Write
Reset
0 0 0 0 0 0 0 0
UARTx_C1 field descriptions
Field Description
7
LOOPS
Loop Mode Select
When LOOPS is set, the RxD pin is disconnected from the UART and the transmitter output is internally
connected to the receiver input. The transmitter and the receiver must be enabled to use the loop function.
0 Normal operation.
1 Loop mode where transmitter output is internally connected to receiver input. The receiver input is
determined by RSRC.
6
UARTSWAI
UART Stops in Wait Mode
0 UART clock continues to run in Wait mode.
1 UART clock freezes while CPU is in Wait mode.
5
RSRC
Receiver Source Select
This field has no meaning or effect unless the LOOPS field is set. When LOOPS is set, the RSRC field
determines the source for the receiver shift register input.
0 Selects internal loop back mode. The receiver input is internally connected to transmitter output.
1 Single wire UART mode where the receiver input is connected to the transmit pin input signal.
4
M
9-bit or 8-bit Mode Select
This field must be set when C7816[ISO_7816E] is set/enabled.
0 Normal—start + 8 data bits (MSB/LSB first as determined by MSBF) + stop.
1 Use—start + 9 data bits (MSB/LSB first as determined by MSBF) + stop.
3
WAKE
Receiver Wakeup Method Select
Determines which condition wakes the UART:
• Address mark in the most significant bit position of a received data character, or
• An idle condition on the receive pin input signal.
Table continues on the next page...
Memory map and registers
K22F Sub-Family Reference Manual, Rev. 4, 08/2016
1226 NXP Semiconductors