NXP Semiconductors K22F series, Reference Manual, Page: 707 / 1407

32-Bit Port
Memory
16-Bit Port
Memory
8-Bit Port
Memory
Byte 3 Byte 2 Byte 1 Byte 0
Driven with
address values
Driven with
address values
Byte 1 Byte 0
Byte 3 Byte 2
Byte 0
Byte 1
Byte 2
Byte 3
External Data Bus
Byte Select
FB_AD[31:24] FB_AD[23:16]
FB_AD15:8] FB_AD[7:0]
FB_BE23_16 FB_BE31_24
FB_BE31_24
FB_BE31_24 FB_BE23_16 FB_BE15_8 FB_BE7_0
In BLS=1 mode, the byte enable that corresponds to a given byte lane,
depends on the port size that you are using.
Figure 31-2. Connections for external memory port sizes (CSCRn[BLS] = 1)
31.4.9 Address/data bus multiplexing
FlexBus supports a single 32-bit wide multiplexed address and data bus (FB_AD31–
FB_AD0). FlexBus always drives the full 32-bit address on the first clock of a bus cycle.
During the data phase, the FB_AD31– FB_AD0 lines used for data are determined by the
programmed port size and BLS setting for the corresponding chip-select. FlexBus
continues to drive the address on any FB_AD31– FB_AD0 lines not used for data.
31.4.9.1 FlexBus multiplexed operating modes for CSCRn[BLS]=0
This table shows the supported combinations of address and data bus widths when
CSCRn[BLS] is 0b.
Port size and phase
FB_AD
31–24 23–16 15–8 7–0
32-bit
Address phase Address
Data phase Data
16-bit
Address phase Address
Data phase Data Address
Table continues on the next page...
Chapter 31 External Bus Interface (FlexBus)
K22F Sub-Family Reference Manual, Rev. 4, 08/2016
NXP Semiconductors 707