NXP Semiconductors K22F series, Reference Manual, Page: 1192 / 1407

I2Cx_FLT field descriptions (continued)
Field Description
The following scenario explains the holdoff functionality:
1. The I2C module is configured for a basic transfer, and the SHEN bit is set to 1.
2. A transfer begins.
3. The MCU signals the I2C module to enter stop mode.
4. The byte currently being transferred, including both address and data, completes its transfer.
5. The I2C slave or master acknowledges that the in-transfer byte completed its transfer and
acknowledges the request to enter stop mode.
6. After receiving the I2C module's acknowledgment of the request to enter stop mode, the MCU
determines whether to shut off the I2C module's clock.
If the SHEN bit is set to 1 and the I2C module is in an idle or disabled state when the MCU signals to enter
stop mode, the module immediately acknowledges the request to enter stop mode.
If SHEN is cleared to 0 and the overall data transmission or reception that was suspended by stop mode
entry was incomplete: To resume the overall transmission or reception after the MCU exits stop mode,
software must reinitialize the transfer by resending the address of the slave.
If the I2C Control Register 1's IICIE bit was set to 1 before the MCU entered stop mode, system software
will receive the interrupt triggered by the I2C Status Register's TCF bit after the MCU wakes from the stop
mode.
0 Stop holdoff is disabled. The MCU's entry to stop mode is not gated.
1 Stop holdoff is enabled.
6
STOPF
I2C Bus Stop Detect Flag
Hardware sets this bit when the I2C bus's stop status is detected. The STOPF bit must be cleared by
writing 1 to it.
NOTE: The stop flag is only for the matched slave devices, therefore the master will not respond for it.
0 No stop happens on I2C bus
1 Stop detected on I2C bus
5
SSIE
I2C Bus Stop or Start Interrupt Enable
This bit enables the interrupt for I2C bus stop or start detection.
NOTE: To clear the I2C bus stop or start detection interrupt: In the interrupt service routine, first clear the
STOPF or STARTF bit by writing 1 to it, and then clear the IICIF bit in the status register. If this
sequence is reversed, the IICIF bit is asserted again.
0 Stop or start detection interrupt is disabled
1 Stop or start detection interrupt is enabled
4
STARTF
I2C Bus Start Detect Flag
Hardware sets this bit when the I2C bus's start status is detected. The STARTF bit must be cleared by
writing 1 to it.
0 No start happens on I2C bus
1 Start detected on I2C bus
FLT I2C Programmable Filter Factor
Controls the width of the glitch, in terms of I2C module clock cycles, that the filter must absorb. For any
glitch whose size is less than or equal to this width setting, the filter does not allow the glitch to pass.
Table continues on the next page...
Memory map/register definition
K22F Sub-Family Reference Manual, Rev. 4, 08/2016
1192 NXP Semiconductors