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Appendix C
Status Reporting System
Status Register Structure
Issuing the
command will clear all bits from the status byte register.
Table C-1
Status Bit Definitions of Status Byte (STB)
Bit
Position
Name
Description
0 to 3
Not used
Always 0
4
MAV (Message Available)
Set to “1” when the output queue contains data; reset to
“0” when all of the data has been retrieved.
5
Standard Event Status Register
Summary
Set to “1” when one of the enabled bits in the status event
status register is set to “1.”
6
RQS (Request Status) bit for
SPOLL
MSS (Master Summary Status)
bit for
Set to “1” when any of the status byte register bits enabled
by the service request enable register is set to “1”; reset to
“0” when all of the data has been retrieved through serial
polling.
7
Operation Status Register
Summary
Set to “1” when one of the enabled bits in the operational
status register is set to “1.”