Infineon TLE984 QX Series, User Manual

Page: 86 / 972

User Manual 86 Rev. 1.1
2019-03-18
TLE984xQX
Microcontroller with LIN and Power Switches for Automotive Applications
System Control Unit - Digital Modules (SCU-DM)
7.2.2 SCU Register Overview
This chapter contains an overview of all SCU Registers.
7.2.2.1 Register Map
Table 30 lists the addresses of the SCU SFRs.
Table 29 shows the SCU module base address.
Table 29 Register Address Space
Module Base Address End Address Note
SCU 5000 5000
H
5000 5FFF
H
Table 30 Register Overview SCU Module
Register Short Name
Register Long Name Offset Address Reset Value
SCU_NMISRCLR NMI Status Clear Register 000
H
see Table 82
SCU_IRCON0 Interrupt Request Register 0 004
H
see Table 67
SCU_IRCON1 Interrupt Request Register 1 008
H
see Table 69
SCU_IRCON2 Interrupt Request Register 2 00C
H
see Table 71
SCU_IRCON3 Interrupt Request Register 3 010
H
see Table 73
SCU_IRCON4 Interrupt Request Register 4 014
H
see Table 75
SCU_NMISR NMI Status Register 018
H
see Table 81
SCU_IEN0 Interrupt Enable Register 0 01C
H
see Table 61
SCU_VTOR Vector Table Reallocation Register 020
H
see Table 62
SCU_NMICON NMI Control Register 024
H
see Table 63
SCU_EXICON0 External Interrupt Control Register 0 028
H
see Table 64
SCU_EXICON1 External Interrupt Control Register 1 02C
H
see Table 65
SCU_MODIEN1 Peripheral Interrupt Enable Register 1 030
H
see Table 83
SCU_MODIEN2 Peripheral Interrupt Enable Register 2 034
H
see Table 84
SCU_MODIEN3 Peripheral Interrupt Enable Register 3 038
H
see Table 85
SCU_MODIEN4 Peripheral Interrupt Enable Register 4 03C
H
see Table 86
SCU_PMCON0 Power Mode Control Register 0 040
H
see Table 56
SCU_PLL_CON PLL Control Register 044
H
see Table 41
SCU_CMCON1 Clock Control Register 1 048
H
see Table 42
SCU_CMCON2 Clock Control Register 2 04C
H
see Table 43
Reserved Reserved 050
H
Reserved
SCU_APCLK_CTRL Analog Peripheral Clock Control Register 054
H
see Table 45
SCU_APCLK Analog Peripheral Clock Register 058
H
see Table 46
SCU_APCLK_STS Analog Peripheral Clock Status Register 05C
H
see Table 50
SCU_PMCON Peripheral Management Control Register 060
H
see Table 98
SCU_APCLK_SCLR Analog Peripheral Clock Status Clear Register 064
H
see Table 51
SCU_RSTCON Reset Control Register 068
H
see Table 54