User Manual
697
Rev. 1.1
2019-03-18
TLE984xQX
Microcontroller with LIN and Power Switches for Automotive Applications
Measurement Core Module (incl. ADC2)
23.4
Channel Controller
23.4.1
Functional Description
The task of each channel controller is a prioritization of the individual measurement channels. The
sequencing scheme is illustrated in the example of following table and can be programmed individually for
measurement unit.
The sequence registers SQ
n
and define the time sequence of the measurement channels by the following rules:
• The sequence registers define the measurement sequence and are evaluated from sequence 1 to 7 and for
each register from MSB to LSB, which defines a max. overall measurement periodicity of 49 sampling and
conversion cycles.
• If the individual bit in the sequence register is set to ’1’, the corresponding channel is measured.
• If the individual bit in the sequence register is not set, this measurement phase is skipped.
In the upper example, the resulting channel sequence is defined as:
CH5, CH4, CH2, CH1, CH0, CH6, CH3, CH5, CH4, CH2, CH1,......, CH5, CH4, CH2, CH1, CH0.
In TLE984xQX Channels 0 - 6 can not be programmed by the user. All Sequence registers, especially for high
priority channels are protected to ensure a fast update of measurement results used for internal system
diagnosis. The overall periodicity is mainly determined by this two channels. The channels 0-6 are measured
depending on the amount of ’1’ bits, written in the sequence registers. The following equations can be used
to calculate the periodicity of the required channel measurement.
The overall measurement periodicity of all measurements in A/D conversion cycles is defined as:
(23.1)
The average measurement periodicity of channel n in A/D conversion cycles is defined as
Table 370 Measurement channel sequence definition example (used as default sequence)
Measurement channel n
CH6
CH5
CH4
CH3
CH2
CH1
LSB
CH0
Registers {SQ
_1_4
[6:0]}
0
1
1
0
1
1
1
Registers {SQ
_1_4
[14:8]}
1
0
0
1
0
0
0
Registers {SQ
_1_4
[22:16]}
0
1
1
0
1
1
0
Registers {SQ
_1_4
[30:24]}
1
0
0
1
0
0
1
Registers {SQ_
5_8
[6:0]}
0
1
1
0
1
1
0
Registers {SQ_
5_8
[14:8]}
1
0
0
1
0
0
0
Registers {SQ_
5_8
[22:16]}
0
1
1
0
1
1
1
[ ]
⎟
⎠
⎞
⎜
⎝
⎛
∑
=
6
0
n
m
n
SQ
∑
=
7
1
m
Nmeas
=
