User Manual
136
Rev. 1.1
2019-03-18
TLE984xQX
Microcontroller with LIN and Power Switches for Automotive Applications
System Control Unit - Digital Modules (SCU-DM)
Figure 35 Interrupt Request Generation of External and Peripheral Interrupts
7.6.1.2
Extended Interrupts
Extended interrupts are for non-core on-chip peripherals for core-external trigger of interrupt requests to the
core. There are nine such interrupt.
Interrupt signals from such on-chip peripherals are pulse triggered and active for two clock cycles. These
interrupt signals belonging to the same interrupt node will be latched as one direct interrupt request to the
core. IRCONx (where x = 0-1, 3-4) or peripheral registers hold the interrupt event flags for these extended and
external interrupt events. Corresponding bits in the Interrupt Enable Registers (IEN) within the core may block
or transfer these interrupt requests to the core interrupt controller. An enabled interrupt request is
acknowledged when the core vectors to the interrupt routine. The software routine should clear the interrupt
flags in the IRCONx registers.
As there are more peripheral interrupts than interrupt nodes supported by the core, some interrupts are
multiplexed to the same interrupt node. Where possible and necessary, critical peripheral interrupts (e.g. SC)
have their own dedicated interrupt node.
7.6.2
Interrupt Node Assignment
shows the interrupt node assignment for TLE984xQX.
Table 57 NMI
Interrupt
Node
Vector Address
Assignment for TLE984xQX
NMI
0000
H
PLL, NVM Operation Complete, CLKWDT, Oscillator Watchdog, NVM
map error, ECC error, Pre-Warn SUPP, Pre-Warn TEMP
Table 58 Interrupt
Vector
Table
Service Request
Node ID
Description
GPT1
0
GPT1 interrupt (T2-T4)
GPT2
1
GPT2 interrupt (T5-T6, CR)
MU
2
MU interrupt / ADC2, VBG interrupt
INTx
IEN0/1
EXINTx
EXICON0/1/2
EXINTx
IRCONy
EINTx
SCU
