User Manual
663
Rev. 1.1
2019-03-18
TLE984xQX
Microcontroller with LIN and Power Switches for Automotive Applications
High-Speed Synchronous Serial Interface SSC1/SSC2
not actively driven onto the line, but only held through the pull-up device, the selected slave can pull this
line actively to a low-level when transmitting a zero bit. The master selects the slave device from which it
expects data either by separate select lines or by sending a special command to this slave.
After performing the necessary initialization of the SSC, the serial interfaces can be enabled. For a master
device, the alternate clock line will now go to its programmed polarity. The alternate data line will go to either
0 or 1 until the first transfer starts. After a transfer, the alternate data line will always remain at the logic level
of the last transmitted data bit.
When the serial interfaces are enabled, the master device can initiate the first data transfer by writing the
transmit data into register TB. This value is copied into the shift register (assumed to be empty at this time),
and the selected first bit of the transmit data will be placed onto the TXD line on the next clock from the baud-
rate generator (transmission starts only if CON.EN = 1). Depending on the selected clock phase, a clock pulse
will also be generated on the MS_CLK line. At the same time, with the opposite clock edge, the master latches
and shifts in the data detected at its input line RXD. This “exchanges” the transmit data with the receive data.
Because the clock line is connected to all slaves, their shift registers will be shifted synchronously with the
master’s shift register — shifting out the data contained in the registers, and shifting in the data detected at
the input line. After the preprogrammed number of clock pulses (via the data width selection), the data
transmitted by the master is contained in all the slaves’ shift registers, while the master’s shift register holds
the data of the selected slave. In the master and all slaves, the contents of the shift register are copied into the
receive buffer RB and the receive interrupt line RIR is activated.
A slave device will immediately output the selected first bit (MSB or LSB of the transfer data) at line RXD when
the contents of the transmit buffer are copied into the slave's shift register. Bit CON.BSY is not set until the first
clock edge at SS_CLK appears. The slave device will not wait for the next clock from the baud-rate generator,
as the master does. The reason for this is that, depending on the selected clock phase, the first clock edge
generated by the master may already be used to clock in the first data bit. Thus, the slave’s first data bit must
already be valid at this time.
Note:
On the SSC, a transmission
and
a reception takes place at the same time, regardless of whether
valid data has been transmitted or received.
Note:
The initialization of the CLK pin on the master requires some attention in order to avoid undesired
clock transitions, which may disturb the other devices. Before the clock pin is switched to output via
the related direction control register, the clock output level will be selected in the control register
CON and the alternate output be prepared via the related ALTSEL register, or the output latch must
be loaded with the clock idle level.
