Infineon TLE984 QX Series, User Manual

Page: 105 / 972

User Manual 105 Rev. 1.1
2019-03-18
TLE984xQX
Microcontroller with LIN and Power Switches for Automotive Applications
System Control Unit - Digital Modules (SCU-DM)
OSC2L 3 r OSC-Too-Low Condition Flag
The Oscillator Watchdog monitors the f
OSC.
On OSC-too-low detection (OSC2L: 0 → 1) and VCOBYP = 1
and OSCSS = 01, PLL switches to freerunning mode.
On above condition, and when
f
OSC
is selected as the
system clock source, hardware switches the system clock
source to PLL (
SCU_SYSCON0 .SYSCLKSEL is also
updated).
Note: OWD NMI request is activated on OSC-too-low
condition only in two cases: 1) when
VCOBYP = 1 and OSCSS = 01 and SYSCLKSEL
selects PLL clock as system clock source; 2)
when SYSCLKSEL selects f
OSC
as system clock
source.
0
B
f
OSC
is above threshold.
1
B
f
OSC
is below threshold.
OSCWDTRST 2 rwh1 Oscillator Watchdog Reset
Setting this bit will reset the OSC2L status flag to 1 and
restart the oscillator detection. This bit will be
automatically reset to 0 and thus always be read back as 0.
0
B
No effect.
1
B
Reset OSC2L flag and restart the oscillator watchdog
of the PLL.
OSCSS 1:0 rwpw Oscillator Source Select
This is a PASSWD protected bit. When the protection
scheme (see
Chapter 7.14 ) is activated (default), this bit
cannot be written directly.
Notes
1. Synchronous switching of clock source to internal
oscillator is not possible when XPD = 1 or no external
clock is available (check bit OSC2L).
2. Use the 1X option only when the external clock is not
available.
00
B
PLL internal oscillator OSC_PLL ( f
INT
) is selected
synchronously as f
R
.
01
B
XTAL ( f
OSC
from OSC_HP) is selected synchronously
as f
R
.
1x
B
PLL internal oscillator OSC_PLL ( f
INT
) is selected
asynchronously as f
R
.
Table 40 RESET of SCU_OSC_CON
Register Reset Type Reset Values Reset Short Name Reset Mode Note
RESET_TYPE_4 00000010
H
RESET_TYPE_4
Field Bits Type Description