User Manual
468
Rev. 1.1
2019-03-18
TLE984xQX
Microcontroller with LIN and Power Switches for Automotive Applications
General Purpose Timer Units (GPT12)
Note:
The timing requirements for external input signals can be found in
summarizes the module interface signals, including pins.
16.4.1
GPT2 Core Timer T6 Control
The current contents of the core timer T6 are reflected by its count register T6. This register can also be written
to by the CPU, for example, to set the initial start value.
The core timer T6 is configured and controlled via its control register T6CON.
Timer T6 Run Control
The core timer T6 can be started or stopped by software through bit T6R (timer T6 run bit). This bit is relevant
in all operating modes of T6. Setting bit T6R will start the timer, clearing bit T6R stops the timer.
In Gated Timer Mode, the timer will only run if T6R = 1 and the gate is active (high or low, as programmed).
Note:
When bit T5RC in timer control register T5CON is set, bit T6R will also control (start and stop) the
Auxiliary Timer T5.
Count Direction Control
The count direction of the GPT2 timers (core timer and auxiliary timer) can be controlled either by software or
by the external input pin TxEUD (Timer Tx External Up/Down Control Input). These options are selected by bits
TxUD and TxUDE in the respective control register TxCON. When the up/down control is provided by software
(bit TxUDE = 0), the count direction can be altered by setting or clearing bit TxUD. When bit TxUDE = 1, pin
TxEUD is selected to be the controlling source of the count direction. However, bit TxUD can still be used to
reverse the actual count direction, as shown in
. The count direction can be changed regardless of
whether or not the timer is running.
Note:
When pin TxEUD is used as external count direction control input, it must be configured as input.
Timer T6 Output Toggle Latch
The overflow/underflow signal of timer T6 is connected to a block named ‘Toggle Latch’, shown in the Timer
Mode diagrams.
illustrates the details of this block. An overflow or underflow of T6 will clock two
latches: The first latch represents bit T6OTL in control register T6CON. The second latch is an internal latch
toggled by T6OTL’s output. Both latch outputs are connected to the input control block of the auxiliary timer
T5. The output level of the shadow latch will match the output level of T6OTL, but is delayed by one clock
cycle. When the T6OTL value changes, this will result in a temporarily different output level from T6OTL and
the shadow latch, which can trigger the selected count event in T5.
When software writes to T6OTL, both latches are set or cleared simultaneously. In this case, both signals to the
auxiliary timers carry the same level and no edge will be detected. Bit T6OE (overflow/underflow output
enable) in register T6CON enables the state of T6OTL to be monitored via an external pin T6OUT. When T6OTL
is linked to an external port pin (must be configured as output), T6OUT can be used to control external HW. If
T6OE = 1, pin T6OUT outputs the state of T6OTL. If T6OE = 0, pin T6OUT outputs a high level (while it selects
the timer output signal).
As can be seen from
, when latch T6OTL is modified by software to determine the state of the
output line, also the internal shadow latch is set or cleared accordingly. Therefore, no trigger condition is
detected by T5 in this case.
