User Manual
661
Rev. 1.1
2019-03-18
TLE984xQX
Microcontroller with LIN and Power Switches for Automotive Applications
High-Speed Synchronous Serial Interface SSC1/SSC2
Note:
Only one SSC (etc.) can be master at a given time.
The transfer of serial data bits can be programmed in many respects:
• The data width can be specified from 2 bits to 16 bits
• A transfer may start with either the LSB or the MSB
• The shift clock may be idle low or idle high
• The data bits may be shifted with the leading edge or the trailing edge of the shift clock signal
• The baud rate may be set from 305.18 Baud up to 20 MBaud (@ 40 MHz module clock)
• The shift clock can be generated (MS_CLK) or can be received (SS_CLK)
These features allow the adaptation of the SSC to a wide range of applications requiring serial data transfer.
The Data Width Selection supports the transfer of frames of any data length, from 2-bit “characters” up to 8-
bit “characters”. Starting with the LSB (CON.HB = 0) allows communication with SSC devices in Synchronous
Mode or with 8051 like serial interfaces for example. Starting with the MSB (CON.HB = 1) allows operation
compatible with the SPI interface.
Regardless of the data width selected and whether the MSB or the LSB is transmitted first, the transfer data is
always right-aligned in registers TB and RB, with the LSB of the transfer data in bit 0 of these registers. The data
bits are rearranged for transfer by the internal shift register logic. The unselected bits of TB are ignored; the
unselected bits of RB will not be valid and should be ignored by the receiver service routine.
The Clock Control allows the adaptation of transmit and receive behavior of the SSC to a variety of serial
interfaces. A specific shift clock edge (rising or falling) is used to shift out transmit data, while the other shift
clock edge is used to latch in receive data. Bit CON.PH selects the leading edge or the trailing edge for each
function. Bit CON.PO selects the level of the shift clock line in the idle state. Thus, for an idle-high clock, the
leading edge is a falling one, a 1-to-0 transition (see
Figure 178 Serial Clock Phase and Polarity Options
21.3.3
Full-Duplex Operation
The various devices are connected through three lines. The definition of these lines is always determined by
the master: the line connected to the master’s data output line TXD is the transmit line; the receive line is
connected to its data input line RXD; the shift clock line is either MS_CLK or SS_CLK. Only the device selected
Shift Clock
MS_CLK/SS_CLK
CON.
PH
CON.
PO
1
0
0
0
1
1
1
0
Pins
MTSR/MRST
Transmit Data
Shift Data
Latch Data
First
Bit
Last
Bit
