User Manual
441
Rev. 1.1
2019-03-18
TLE984xQX
Microcontroller with LIN and Power Switches for Automotive Applications
General Purpose Timer Units (GPT12)
Timer T3 in Counter Mode
Counter Mode for the core timer T3 is selected by setting bitfield T3M in register T3CON to 001
B
. In Counter
Mode, timer T3 is clocked by a transition at the external input pin T3IN. The event causing an increment or
decrement of the timer can be a positive, a negative, or both a positive and a negative transition at this line.
Bitfield T3I in control register T3CON selects the triggering transition (see
).
Figure 89 Block Diagram of Core Timer T3 in Counter Mode
For Counter Mode operation, pin T3IN must be configured as input. The maximum input frequency allowed in
Counter Mode depends on the selected prescaler value. To ensure that a transition of the count input signal
applied to T3IN is recognized correctly, its level must be held high or low for a minimum number of module
clock cycles before it changes. This information can be found in
MCB05393
Core Timer T3
Toggle Latch
MUX
Up/Down
0
1
T3EUD
T3IN
=1
T3UD
T3R
Count
T3OUT
T3IRQ
to
T2/T4
T3UDE
T3I
Edge
Select
