User Manual
658
Rev. 1.1
2019-03-18
TLE984xQX
Microcontroller with LIN and Power Switches for Automotive Applications
High-Speed Synchronous Serial Interface SSC1/SSC2
21
High-Speed Synchronous Serial Interface SSC1/SSC2
21.1
Features
• Master and Slave Mode operation
– Full-duplex or half-duplex operation
• Transmit and receive double buffered
• Flexible data format
– Programmable number of data bits: 2 to 16 bits
– Programmable shift direction: Least Significant Bit (LSB) or Most Significant Bit (MSB) shift first
– Programmable clock polarity: idle low or high state for the shift clock
– Programmable clock/data phase: data shift with leading or trailing edge of the shift clock
• Variable baud rate, e.g. 250kBaud - 8MBaud
• Compatible with Serial Peripheral Interface (SPI)
• Interrupt generation
– On a transmitter empty condition
– On a receiver full condition
– On an error condition (receive, phase, baud rate, transmit error)
– On a transfer complete condition
• Port direction selection, see
21.2
Introduction
The High-Speed Synchronous Serial Interface (SSC) supports both full-duplex and half-duplex serial
synchronous communication. The serial clock signal can be generated by the SSC internally (master mode),
using its own 16-Bit baud-rate generator, or can be received from an external master (slave mode). Data width,
shift direction, clock polarity, and phase are programmable. This allows communication with SPI-compatible
devices or devices using other synchronous serial interfaces.
Data is transmitted or received on lines TXD and RXD, which are normally connected to the pins MTSR
(MasterTransmit/Slave Receive) and MRST (Master Receive/Slave Transmit). The clock signal is output via line
MS_CLK (Master Serial Shift Clock) or input via line SS_CLK (Slave Serial Shift Clock). Both lines are normally
connected to the pin SCLK. Transmission and reception of data are double-buffered.
