User Manual
666
Rev. 1.1
2019-03-18
TLE984xQX
Microcontroller with LIN and Power Switches for Automotive Applications
High-Speed Synchronous Serial Interface SSC1/SSC2
21.3.6
Baud Rate Generation
The serial channel SSC has its own dedicated 16-bit baud-rate generator with 16-bit reload capability,
allowing baud rate generation independent of the timers.
shows the baud-rate generator.
shows the baud-rate generator of the SSC in more detail.
Figure 181 SSC Baud-rate Generator
The baud-rate generator is clocked with the module clock
f
hw_clk
. The timer counts downwards. Register BR is
the dual-function Baud-rate Generator/Reload register. Reading BR, while the SSC is enabled, returns the
contents of the timer. Reading BR, while the SSC is disabled, returns the programmed reload value. In this
mode, the desired reload value can be written to BR.
Note:
Never write to BR while the SSC is enabled.
The formulas below calculate either the resulting baud rate for a given reload value, or the required reload
value for a given baud rate:
(21.1)
(21.2)
<BR> represents the contents of the reload register, taken as an unsigned 16-bit integer, while baud rate is
equal to
f
MS_CLK/SS_CLK
as shown in
.
The maximum baud rate that can be achieved when using a module clock of 40 MHz is 20 MBaud in Master
Mode (with <BR> = 0000
H
) or 10 MBaud in Slave Mode (with <BR> = 0001
H
).
lists some possible baud rates together with the required reload values and the resulting bit times,
assuming a module clock of 40 MHz.
Table 348 Typical Baud Rates of the SSC (
f
hw_clk
= 40 MHz)
Reload Value
Baud Rate (=
f
MS_CLK/SS_CLK
)
Deviation
0000
H
20 MBaud (only in Master Mode)
0.0%
0001
H
10 MBaud
0.0%
0013
H
1 MBaud
0.0%
0027
H
500 kBaud
0.0%
2
..
16-Bit Counter
16-Bit Reload Register
f
PCLK
f
MS_CLK/SS_CLK
f
MS_CLK max
in Master Mode
<
f
PCLK
/2
f
SS_CLK max
in Slave Mode
<
f
PCLK
/4
=
Baud rate
2 (<BR> + 1)
f
hw_clk
•
f
hw_clk
BR
=
- 1
•
2 Baud rate