User Manual
660
Rev. 1.1
2019-03-18
TLE984xQX
Microcontroller with LIN and Power Switches for Automotive Applications
High-Speed Synchronous Serial Interface SSC1/SSC2
Figure 177 Synchronous Serial Channel SSC Block Diagram
21.3.2
Operating Mode Selection
The operating mode of the serial channel SSC is controlled by its control register CON. This register serves two
purposes:
• During programming (SSC disabled by CON.EN = 0), it provides access to a set of control bits
• During operation (SSC enabled by CON.EN = 1), it provides access to a set of status flags.
The shift register of the SSC is connected to both the transmit lines and the receive lines via the pin control
logic (see block diagram in
). Transmission and reception of serial data are synchronized and take
place at the same time, i.e. the same number of transmitted bits is also received. Transmit data is written into
the Transmit Buffer (TB) and is moved to the shift register as soon as this is empty. An SSC master (CON.MS = 1)
immediately begins transmitting, while an SSC slave (CON.MS = 0) will wait for an active shift clock. When the
transfer starts, the busy flag CON.BSY is set and the Transmit Interrupt Request line TIR will be activated to
indicate that register TB may be reloaded again. When the programmed number of bits (2 … 16) has been
transferred, the contents of the shift register are moved to the Receive Buffer RB and the Receive Interrupt
Request line RIR will be activated. If no further transfer is to take place (TB is empty), CON.BSY will be cleared
at the same time. Software should not modify CON.BSY, as this flag is hardware controlled.
Note:
The SSC starts transmission and sets CON.BSY minimum two clock cycles after transmit data is
written into TB. Therefore, it is not recommended to poll CON.BSY to indicate the start and end of a
single transmission. Instead, interrupt service routine should be used if interrupts are enabled, or
the interrupt flags IRCON1.TIR and IRCON1.RIR should be polled if interrupts are disabled.
PCLK
SS_CLK
RIR
TIR
EIR
Receive Int. Request
Transmit Int. Request
Error Int. Request
Control
Status
TXD(Master)
RXD(Slave)
MS_CLK
RXD(Master)
TXD(Slave)
Internal Bus
Baud-rate
Generator
Clock
Control
SSC Control Block
Register CON
Pin
Control
16-Bit Shift
Register
Transmit Buffer
Register TB
Receive Buffer
Register RB
Shift
Clock
