Infineon TLE984 QX Series, User Manual

Page: 114 / 972

User Manual 114 Rev. 1.1
2019-03-18
TLE984xQX
Microcontroller with LIN and Power Switches for Automotive Applications
System Control Unit - Digital Modules (SCU-DM)
7.3.6.4 Analog Peripherals Clock Control Registers
The clock frequency for the analog modules is selected via register APCLK. The APCLK is used as operating
clock for all analog peripherals. For this reason it is important to choose always the required frequency range,
if system clock is changed.
Analog Peripheral Clock Control Register
SCU_APCLK_CTRL Offset Reset Value
Analog Peripheral Clock Control Register 054
H
see Table 45
Field Bits Type Description
RES 31:9 r Reserved
Returns 0 if read; should be written with 0.
CLKWDT_IE 8 rwpw Clock Watchdog Interrupt Enable
Returns 0 if read; should be written with 0.
Note: This is a PASSWD protected bit. When the
protection scheme (see
Chapter 7.14 ) is
activated (default), this bit cannot be written
directly.
0
B
Interrupt disabled
1
B
Interrupt enabled
RES 7:1 r Reserved
Returns 0 if read; should be written with 0.
APCLK_SET 0 rwh1 Set and Overtake Flag for Clock Settings
This Flag makes the APCLK1, APCLK2 Settings valid.
Note: If APCLK_SET is cleared by hardware once the clock
setting are overtaken
0
B
Clock Settings are ignored (previous values are held)
1
B
Clock Settings are overtaken
Table 45 RESET of SCU_APCLK_CTRL
Register Reset Type Reset Values Reset Short Name Reset Mode Note
RESET_TYPE_4 00000000
H
RESET_TYPE_4
31 16
r
RES
15 9
r
RES
88
rwpw
CLKW
DT_*
7 1
r
RES
00
rwh1
APCL
K_S*