IBM PPC440X5 CPU Core, User Manual

Page: 337 / 590

lswx
Load String Word Indexed
Preliminary PPC440x5 CPU Core User’s Manual
instrset.fm.
September 12, 2002
Page 337 of 589
lswx
Load String Word Indexed
EA
←
(RA|0) + (RB)
CNT
←
XER[TBC]
n
←
CNT
R
FINAL
←
((RT + CEIL(CNT/4) – 1) % 32)
r
←
RT – 1
i
←
0
do while n > 0
if i = 0 then
r
←
r + 1
if r = 32 then
r
←
0
GPR(r))
←
0
GPR(r)
i:i+7
)
←
MS(EA,1)
i
←
i + 8
if i = 32 then
i
←
0
EA
←
EA + 1
n
←
n – 1
An effective address (EA) is formed by adding an index to a base address. The index is the contents of
register RB. The base address is 0 if the RA field is 0 and is the contents of register RA otherwise.
A byte count CNT is obtained from XER[TBC].
A series of CNT consecutive bytes in main storage, starting at the EA, are loaded into CEIL(CNT/4) consecu-
tive GPRs, four bytes per GPR, until the byte count is exhausted. Bytes are loaded into GPRs; the byte
having the lowest address is loaded into the most significant byte. Bits to the right of the last byte loaded in
the last GPR used are set to 0.
The set of consecutive GPRs loaded starts at register RT, continues through GPR(31), and wraps to register
0, loading until the byte count is exhausted, which occurs in register R
FINAL
.
If XER[TBC] is 0, the byte count is 0 and the contents of register RT are undefined.
If instruction bit 31 contains 1, the contents of CR[CR0] are undefined.
Registers Altered
• RT and subsequent GPRs as described above.
Invalid Instruction Forms
• Reserved fields
• RA or RB is in the range of registers to be loaded.
• RA = RT = 0
lswx RT, RA, RB
31 RT RA RB 533
0 6 11 16 21 31