IBM PPC440X5 CPU Core, User Manual

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User’s Manual
PPC440x5 CPU Core Preliminary
Page 102 of 589
cache.fm.
September 12, 2002
Figure 4-3 and Figure 4-4 illustrate two of these examples of the use of the locking and transient mecha-
nisms. Other configurations are possible, given the ability to program each of the victim limit fields to different
relative values, although some configurations are not necessarily useful or practical.
Figure 4-3. Cache Locking and Transient Mechanism (Example 1)
1
Cache Set n
1
Way w
2
NORMAL LINES
Way NFLOOR
Way TCEILING
TRANSIENT LINES
Way TFLOOR
Way TFLOOR – 1
LOCKED LINES
Way 0
Note 1: This example illustrates partitioning of the cache
into locked, transient, and normal regions with no
overlap. The figure illustrates a single set, but all
sets of the cache are partitioned according to the
same victim limit values.
Note 2: w = 31 for 8KB cache, 63 for 16KB and 32KB
cache.