IBM PPC440X5 CPU Core, User Manual

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User’s Manual
PPC440x5 CPU Core Preliminary
Page 456 of 589
regsummIntro.fm.
September 12, 2002
IVOR14 Interrupt Vector Offset Register 14 0x19E Supervisor Read/Write
IVOR15 Interrupt Vector Offset Register 15 0x19F Supervisor Read/Write
MCSRR0 Machine Check Save Restore Register 0 0x23A Supervisor Read/Write
MCSRR1 Machine Check Save Restore Register 1 0x23B Supervisor Read/Write
MCSR Machine Check Status Register 0x23C Supervisor Read/Write
INV0 Instruction Cache Normal Victim 0 0x370 Supervisor Read/Write
INV1 Instruction Cache Normal Victim 1 0x371 Supervisor Read/Write
INV2 Instruction Cache Normal Victim 2 0x372 Supervisor Read/Write
INV3 Instruction Cache Normal Victim 3 0x373 Supervisor Read/Write
ITV0 Instruction Cache Transient Victim 0 0x374 Supervisor Read/Write
ITV1 Instruction Cache Transient Victim 1 0x375 Supervisor Read/Write
ITV2 Instruction Cache Transient Victim 2 0x376 Supervisor Read/Write
ITV3 Instruction Cache Transient Victim 3 0x377 Supervisor Read/Write
CCR1 Core Configuration Register 1 0x378 Supervisor Read/Write
DNV0 Data Cache Normal Victim 0 0x390 Supervisor Read/Write
DNV1 Data Cache Normal Victim 1 0x391 Supervisor Read/Write
DNV2 Data Cache Normal Victim 2 0x392 Supervisor Read/Write
DNV3 Data Cache Normal Victim 3 0x393 Supervisor Read/Write
DTV0 Data Cache Transient Victim 0 0x394 Supervisor Read/Write
DTV1 Data Cache Transient Victim 1 0x395 Supervisor Read/Write
DTV2 Data Cache Transient Victim 2 0x396 Supervisor Read/Write
DTV3 Data Cache Transient Victim 3 0x397 Supervisor Read/Write
DVLIM Data Cache Victim Limit 0x398 Supervisor Read/Write
IVLIM Instruction Cache Victim Limit 0x399 Supervisor Read/Write
RSTCFG Reset Configuration 0x39B Supervisor Read-only
DCDBTRL Data Cache Debug Tag Register Low 0x39C Supervisor Read-only
DCDBTRH Data Cache Debug Tag Register High 0x39D Supervisor Read-only
ICDBTRL Instruction Cache Debug Tag Register Low 0x39E Supervisor Read-only
ICDBTRH Instruction Cache Debug Tag Register High 0x39F Supervisor Read-only
MMUCR Memory Management Unit Control Register 0x3B2 Supervisor Read/Write
CCR0 Core Configuration Register 0 0x3B3 Supervisor Read/Write
ICDBDR Instruction Cache Debug Data Register 0x3D3 Supervisor Read-only
DBDR Debug Data Register 0x3F3 Supervisor Read/Write
Table 10-2. Special Purpose Registers Sorted by SPR Number
Mnemonic Register Name SPRN Model Access