IBM PPC440X5 CPU Core, User Manual

Page: 149 / 590

User’s Manual
Preliminary PPC440x5 CPU Core
mmu.fm.
September 12, 2002
Page 149 of 589
Store Without Allocate (SWOA) Field
Performance for certain applications can be affected by the allocation of cache lines on store misses. If the
store accesses for a particular application are distributed sparsely in memory, and if the data is typically not
re-used after having been stored, then performance may be improved by avoiding the latency and bus band-
width associated with filling the entire cache line containing the bytes being stored. On the other hand, if an
application typically stores to contiguous locations, or tends to store repeatedly to the same locations or to re-
access data after it has been stored, then performance would likely be improved by allocating the line in the
cache upon the first miss so that subsequent accesses will hit in the cache.
The SWOA field is one of two MMUCR fields which can control the allocation of cache lines upon store
misses. The other is the U2SWOAE field, and if U2SWOAE is 1 then the U2 storage attribute controls the
allocation and the SWOA field is ignored (see User-Definable (U0–U3) on page 147). However, if the
U2SWOAE field is 0, then the SWOA field controls cache line allocation for all cacheable store misses.
Specifically, if a cacheable store access misses in the data cache, then if SWOA is 0, then the cache line will
be filled into the data cache, and the store data will be written into the cache (as well as to memory if the
associated memory page is also marked as write-through; see Write-Through (W) on page 145). Conversely,
if SWOA is 1, then cacheable store misses will not allocate the line in the data cache, and the store data will
be written to memory only, whether or not the write-through attribute is set.
See Instruction and Data Caches on page 95 for more information on cache line allocation on store misses.
U1 Transient Enable (U1TE) Field
When U1TE is 1, then the U1 storage attribute is enabled to control the transient mechanism of the instruc-
tion and data caches (see User-Definable (U0–U3) on page 147). If the U1 field of the TLB entry for the
memory page being accessed is 0, then the access will use the normal portion of the cache. If the U1 field is
1, then the transient portion of cache will be used.
If the U1TE field is 0, then the transient cache mechanism is disabled and all accesses use the normal portion
of the cache.
See Chapter 4, “Instruction and Data Caches” for more information on the transient cache mechanism.
U2 Store Without Allocate Enable (U2SWOAE) Field
An explanation of the allocation of cache lines on store misses is provided in the section on the SWOA field
above. The U2SWOAE field is the other mechanism which can control such allocation. If U2SWOAE is 0,
then the SWOA field determines whether or not a cache line is allocated on a store miss.
When U2SWOAE is 1, then the U2 storage attribute is enabled to control the allocation on a memory page
basis, and the SWOA field is ignored (see User-Definable (U0–U3) on page 147). If the U2 field of the TLB
entry for the memory page containing the bytes being stored is 0, then the cache line will be allocated in the
data cache on a store miss. If the U2 field is 0, then the cache line will not be allocated.
See Chapter 4, “Instruction and Data Caches” for more information on cache line allocation on store misses.
Data Cache Unlock Exception Enable (DULXE) Field
The DULXE field can be used to force a Cache Locking exception type Data Storage interrupt to occur if a
dcbf instruction is executed in user mode (MSR[PR]=1). Since dcbf can be executed in user mode and since
it causes a cache line to be flushed from the data cache, it has the potential for allowing an application