IBM PPC440X5 CPU Core, User Manual

Page: 131 / 590

User’s Manual
Preliminary PPC440x5 CPU Core
cache.fm.
September 12, 2002
Page 131 of 589
If the CCR1[DCMPEI] bit is set, the parity for any modified (dirty) bits that are written, either during the
process of a line fill or by execution of a store instruction or
dcbz, is set to odd parity. If the CCR1[FFF] bit is
also set in addition to CCR1[DCMPEI], then the parity for all four modified (dirty) bits is set to odd parity. Store
access to a cache line that is already in the cache and in a memory page for which the write-through storage
attribute is set does not update the modified (dirty bits) nor the modified (dirty) parity bits, so for these
accesses the CCR1[DCMPEI] setting has no effect.
The CCR1[FCOM] (Force Cache Operation Miss) bit enables the simulation of a multi-hit parity error. When
set, it will cause an dcbt to appear to be a miss, initiating a line fill, even if the line is really already in the
cache. Thus, this bit allows the same line to be filled to the cache multiple times, which will generate a multi-
hit parity error when an attempt is made to read data from those cache lines. The following pseudocode is an
example of how to use the CCR1[FCOM] field to simulate a multi-hit parity error in the data cache:
mtspr CCR0, Rx ; set CCR0[GDCBT]
dcbt <target line address> ; this dcbt fills a first copy of the target line, if necessary
msync ; wait for the fill to finish
mtspr CCR1, Ry ; set CCR1[FCOM]
isync ; wait for the CCR1 context to update
dcbt <target line address> ; fill a second copy of the target line
msync ; wait for the fill to finish
mtspr CCR1, Rz ; reset CCR1[FCOM]
isync ; wait for the CCR1 context to update
br <byte 0 of target line> ; load byte causes interrupt