IBM PPC440X5 CPU Core, User Manual

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User’s Manual
PPC440x5 CPU Core Preliminary
Page 182 of 589
intrupts.fm.
September 12, 2002
instructions not with the execution of instructions. Data Storage
exceptions and Data TLB Miss exceptions are associated with the
execution of instruction cache management instructions, as well as
with the execution of load, store, and data cache management
instructions.
Write Access Control exception
A Write Access Control exception is caused by one of the following:
• While in user mode (MSR[PR] = 1), a store, dcbz, or dcbi instruction attempts to access a location in
storage that is not enabled for write access in user mode (that is, the TLB entry associated with the
memory page being accessed has UW=0).
• While in supervisor mode (MSR[PR] = 0), a store, dcbz, or dcbi instruction attempts to access a
location in storage that is not enabled for write access in supervisor mode (that is, the TLB entry
associated with the memory page being accessed has SW=0).
Byte Ordering exception
A Byte Ordering exception will occur when a floating-point unit or auxiliary processor is
attached to the PPC440x5 core, and a floating-point or auxiliary processor load or store
instruction attempts to access a memory page with a byte order which is not supported by
the attached processor. Whether or not a given load or store instruction type is supported for
a given byte order is dependent on the implementation of the floating-point or auxiliary pro-
cessor. All integer load and store instructions supported by the PPC440x5 core are
supported for both big endian and little endian memory pages.
Cache Locking exception
A Cache Locking exception is caused by one of the following:
• While in user mode (MSR[PR] = 1) with MMUCR[IULXE]=1, execution of an icbi instruction is
attempted. The exception occurs whether or not the cache line targeted by the icbi instruction is
actually locked in the instruction cache.
• While in user mode (MSR[PR] = 1) with MMUCR[DULXE]=1, execution of a dcbf instruction is
attempted. The exception occurs whether or not the cache line targeted by the dcbf instruction is
actually locked in the data cache.
See Chapter 4, “Instruction and Data Caches” and Memory Management Unit Control Regis-
ter (MMUCR) on page 148 for more information on cache locking and Cache Locking
exceptions, respectively.
If a stwcx. instruction causes a Write Access Control exception, but the processor does not have the reserva-
tion from a lwarx instruction, then a Data Storage interrupt does not occur and the instruction completes,
updating CR[CR0] to indicate the failure of the store due to the lost reservation.
If a Data Storage exception occurs on any of the following instructions, then the instruction is treated as
a no-op, and a Data Storage interrupt does not occur.
•
lswx or stswx with a length of zero (although the target register of lswx will still be undefined, as it is
whether or not a Data Storage exception occurs)
• icbt
• dcbt