IBM PPC440X5 CPU Core, User Manual

Page: 53 / 590

User’s Manual
Preliminary PPC440x5 CPU Core
prgmodel.fm.
September 12, 2002
Page 53 of 589
2.2.1.4 Machine State Register
The Machine State Register (MSR) is a register of its own unique type that controls important chip functions,
such as the enabling or disabling of various interrupt types.
The MSR can be written from a GPR using the
mtmsr instruction. The contents of the MSR can be read into
a GPR using the
mfmsr instruction. The MSR[EE] bit can be set or cleared atomically using the wrtee or
wrteei instructions. The MSR contents are also automatically saved, altered, and restored by the interrupt-
handling mechanism. See Machine State Register (MSR) on page 165 for more detailed information on the
MSR and the function of each of its bits.
2.2.1.5 Device Control Registers
Device Control Registers (DCRs) are on-chip registers that exist architecturally and physically outside the
PPC440x5 core, and thus are not specified by the Book-E Enhanced PowerPC Architecture, nor by this
user’s manual for the PPC440x5 core. Rather, PowerPC Book-E simply defines the existence of the DCR
address space and the instructions that access the DCRs, and does not define any particular DCRs. The
DCR access instructions are
mtdcr (move to device control register) and mfdcr (move from device control
register), which move data between GPRs and the DCRs.
DCRs may be used to control various on-chip system functions, such as the operation of on-chip buses,
peripherals, and certain processor core behaviors.
2.3 Instruction Classes
PowerPC Book-E architecture defines all instructions as falling into exactly one of the following four classes,
as determined by the primary opcode (and the extended opcode, if any):
1. Defined
2. Allocated
3. Preserved
4. Reserved (-illegal or -nop)
2.3.1 Defined Instruction Class
This class of instructions consists of all the instructions defined in PowerPC Book-E. In general, defined
instructions are guaranteed to be supported within a PowerPC Book-E system as specified by the architec-
ture, either within the processor implementation itself or within emulation software supported by the system
operating software.
One exception to this is that, for implementations (such as the PPC440x5) that only provide the 32-bit subset
of PowerPC Book-E, it is not expected (and likely not even possible) that emulation of the 64-bit behavior of
the defined instructions will be provided by the system.
As defined by PowerPC Book-E, any attempt to execute a defined instruction will:
• cause an Illegal Instruction exception type Program interrupt, if the instruction is not recognized by the
implementation; or
• cause an Unimplemented Instruction exception type Program interrupt, if the instruction is recognized by
the implementation and is not a floating-point instruction, but is not supported by the implementation; or