IBM PPC440X5 CPU Core, User Manual

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User’s Manual
PPC440x5 CPU Core Preliminary
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cache.fm.
September 12, 2002
set instead of just the one corresponding dirty bit). When a data cache line is flushed, the type of request
made to the data write PLB interface depends upon which dirty bits associated with the line are set, and the
state of the CCR1[FFF] bit. If the CCR1[FFF] bit is set, the request will always be for an entire 32-byte line.
Most users will leave the CCR1[FFF] reset to zero, in which case the controller minimizes the size of the
transfer by the following algorithm. If only one dirty bit is set, the request type will be for a single doubleword
write. If only two dirty bits are set, and they are in the same quadword, then the request type will be for a 16-
byte line write. If two or more dirty bits are set, and they are in different quadwords, the request type will be for
an entire 32-byte line write. Regardless of the type of request generated by a cache line flush, the address is
always specified as the first byte of the request.
If a store access occurs to a cache line in a memory page for which the write-through storage attribute is set,
the dirty bits for that cache line do not get updated, since such a store access will be written directly to
memory (and into the data cache as well, if the access is either a hit or if the cache line is allocated upon a
miss).
On the other hand, it is permissible for there to exist multiple TLB entries that map to the same real memory
page, but specify different values for the write-through storage attribute. In this case, it is possible for a store
operation to a virtual page which is marked as non-write-through to have caused the cache line to be marked
as dirty, so that a subsequent store operation to a different virtual page mapped to the same real page but
marked as write-through encounters a dirty line in the data cache. If this happens, the store to the write-
through page will write the data for the store to both the data cache and to memory, but it will not modify the
dirty bits for the cache line.
4.3.1.5 Data Read PLB Interface Requests
When a PLB read request results from an access to a cacheable memory location, the request is always for a
32-byte line read, regardless of the type and size of the access that prompted the request. The address
presented will be for the first byte of the target of the access.
On the other hand, when a PLB read request results from an access to a caching-inhibited memory location,
only the byte[s] specifically accessed will be requested from the PLB, according to the type of instruction
prompting the access. Based on the type of storage access instructions (including integer, floating-point, and
AP), and based on the mechanism for handling misaligned accesses which cross a quadword boundary (see
“Load and Store Alignment” on page -117), the following types of PLB read requests can occur due to
caching inhibited requests:
• 1-byte read (any byte address 0–15 within a quadword)
• 2-byte read (any byte address 0–14 within a quadword)
• 3-byte read (any byte address 0–13 within a quadword)
• 4-byte read (any byte address 0–12 within a quadword)
• 8-byte read (any byte address 0–8 within a quadword)
This request can only occur due to a doubleword floating-point or AP load instruction
• 16-byte line fill (must be for byte address 0 of a quadword)
This request can only occur due to a quadword AP load instruction