IBM PPC440X5 CPU Core, User Manual

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User’s Manual
Preliminary PPC440x5 CPU Core
intrupts.fm.
September 12, 2002
Page 201 of 589
interrupt may have occurred from within a non-critical class interrupt handler, prior to the non-critical class
interrupt handler having saved SRR0 and SRR1. Therefore, within the critical class interrupt handler, both
pairs of save/restore registers may contain data that is necessary to the system software.
Similarly, the Machine Check handler must avoid further machine checks, as well as both critical and non-crit-
ical interrupts, since the machine check handler may have been called from within a critical or non-critical
interrupt handler.
6.6.2 Interrupt Order
The following is a prioritized listing of the various enabled interrupt types for which exceptions might exist
simultaneously:
1. Synchronous (non-debug) interrupts:
1. Data Storage
2. Instruction Storage
3. Alignment
4. Program
5. Floating-Point Unavailable
6. System Call
7. Auxiliary Processor Unavailable
8. Data TLB Error
9. Instruction TLB Error
Only one of the above types of synchronous interrupts may have an existing exception generating it at
any given time. This is guaranteed by the exception priority mechanism (see Exception Priorities on
page 202) and the requirements of the sequential execution model defined by the PowerPC Book-E
architecture.
2. Machine Check
3. Debug
4. Critical Input
5. Watchdog Timer
6. External Input
7. Fixed-Interval Timer
8. Decrementer
Even though, as indicated above, the non-critical, synchronous exception types listed under item 1 are gener-
ated with higher priority than the critical interrupt types listed in items 2-5, the fact is that these non-critical
interrupts will immediately be followed by the highest priority existing critical interrupt type, without executing
any instructions at the non-critical interrupt handler. This is because the non-critical interrupt types do not
automatically clear MSR[ME,DE,CE] and hence do not automatically disable the critical interrupt types. In all
other cases, a particular interrupt type from the above list will automatically disable any subsequent interrupts
of the same type, as well as all other interrupt types that are listed below it in the priority order.