IBM PPC440X5 CPU Core, User Manual

Page: 41 / 590

User’s Manual
Preliminary PPC440x5 CPU Core
prgmodel.fm.
September 12, 2002
Page 41 of 589
Similarly, the TLB management instructions access page operands, and—as determined by the page size—
the associated low-order effective address bits are ignored during the execution of these instructions.
Instruction storage operands, on the other hand, are always four bytes long, and the effective addresses
calculated by Branch instructions are therefore always word-aligned.
2.1.2 Effective Address Calculation
For a storage access instruction, if the sum of the effective address and the operand length exceeds the
maximum effective address of 2
32
–1 (that is, the storage operand itself crosses the maximum address
boundary), the result of the operation is undefined, as specified by the architecture. The PPC440x5 core
performs the operation as if the storage operand wrapped around from the maximum effective address to
effective address 0. Software, however, should not depend upon this behavior, so that it may be ported to
other implementations that do not handle this scenario in the same fashion. Accordingly, software should
ensure that no data storage operands cross the maximum address boundary.
Note that since instructions are words and since the effective addresses of instructions are always implicitly
on word boundaries, it is not possible for an instruction storage operand to cross any word boundary,
including the maximum address boundary.
Effective address arithmetic, which calculates the starting address for storage operands, wraps around from
the maximum address to address 0, for all effective address computations except next sequential instruction
fetching. See Instruction Storage Addressing Modes on page 41 for more information on next sequential
instruction fetching at the maximum address boundary.
2.1.2.1 Data Storage Addressing Modes
There are two data storage addressing modes supported by the PPC440x5 core:
• Base + displacement (D-mode) addressing mode:
The 16-bit D field is sign-extended and added to the contents of the GPR designated by RA or to zero if
RA = 0; the low-order 32 bits of the sum form the effective address of the data storage operand.
• Base + index (X-mode) addressing mode:
The contents of the GPR designated by RB (or the value 0 for
lswi and stswi) are added to the contents
of the GPR designated by RA, or to 0 if RA = 0; the low-order 32 bits of the sum form the effective
address of the data storage operand.
2.1.2.2 Instruction Storage Addressing Modes
There are four instruction storage addressing modes supported by the PPC440x5 core:
• I-form branch instructions (unconditional):
The 24-bit LI field is concatenated on the right with 0b00, sign-extended, and then added to either the
address of the branch instruction if AA=0, or to 0 if AA=1; the low-order 32 bits of the sum form the effec-
tive address of the next instruction.
• Taken B-form branch instructions: