IBM PPC440X5 CPU Core, User Manual

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User’s Manual
PPC440x5 CPU Core Preliminary
Page 114 of 589
cache.fm.
September 12, 2002
4.2.4.6 Instruction Cache Parity Operations
The instruction cache contains parity bits and multi-hit detection hardware to protect against soft data errors.
Both the instruction tags and data are protected. Instruction cache lines consist of a tag field, 256 bits of data,
and 10 parity bits. The tag field is stored in CAM (Content Addressible Memory) cells, while the data and
parity bits are stored in normal RAM cells. The instruction cache is virtually tagged and indexed, so the tag
field contains a TID field that is compared to the PID value, a TD bit that can be set to disable the TID
comparison for shared pages, and the effective address bits to be compared to the fetch request. The exact
number of effective address bits depends on the specific cache size.
Two types of errors may be detected by the instruction cache parity logic. In the first type, the parity bits
stored in the RAM array are checked against the appropriate data in the instruction cache line when the RAM
line is read for an instruction fetch. Note that a parity error will not be signaled as a result of an
icread instruc-
tion.
The second type of parity error that may be detected is a multi-hit, sometimes referred to as an MHIT. This
type of error may occur when a tag address bit is corrupted, leaving two tags in the instruction cache array
that match the same input address. Multi-hit errors may be deteced on any instruction fetch. No parity errors
of any kind are detected on speculative fetch lookups or
icbt lookups, Rather, such lookups are treated as
cache hits and cause no further action until an instruction fetch lookup at the offending address causes an
error to be detected.
If a parity error is detected, and the MSR[ME] is asserted, (i.e. Machine Check interrupts are enabled), the
processor vectors to the Machine Check interrupt handler. As is the case for any Machine Check interrupt,
after vectoring to the machine check handler, the MCSRR0 contains the value of the oldest “uncommitted”
instruction in the pipeline at the time of the exception and MCSRR1 contains the old Machine Status Register
(MSR) context. The interrupt handler is able to query Machine Check Status Register (MCSR) to find out that
it was called due to a instruction cache parity error, and is then expected to invalidate the I-cache (using
iccci). The handler returns to the interrupted process using the rfmci instruction.
As long as parity checking and machine check interrupts are enabled, instruction cache parity errors are
always recoverable. That is, they are detected and cause a machine check interrupt before the parity error
can cause the machine to update the architectural state with corrupt data. Also note that the machine check
interrupt is asynchronous; that is, the return address in the MCSRR0 does not point at the instruction address
that contains the parity error. Rather, the Machine Check interrupt is taken as soon as the parity error is
detected, and some instructions in progress will get flushed and re-excuted after the interrupt, just as if the
machine were responding to an external interrupt.
4.2.4.7 Simulating Instruction Cache Parity Errors for Software Testing
Because parity errors occur in the cache infrequently and unpredictably, it is desirable to provide users with a
way to simulate the effect of an instruction cache parity error so that interrupt handling software may be exer-
cised. This is exactly the purpose of the CCR1[ICDPEI], CCR1[ICTPEI], and CCR1[FCOM] fields.
23 TD
Translation ID (TID) Disable
0 TID enable
1 TID disable
TID Disable field for the memory page associated
with the cache line read by icread.
24:31 TID Translation ID
TID field portion of the virtual address associated
with the cache line read by icread.