IBM PPC440X5 CPU Core, User Manual

Page: 169 / 590

User’s Manual
Preliminary PPC440x5 CPU Core
intrupts.fm.
September 12, 2002
Page 169 of 589
Programming Note: An MSR bit that is reserved may be altered by rfci, consistent with the
value being restored from CSRR1.
CSRR1 can be written from a GPR using
mtspr, and can be read into a GPR using mfspr.
6.4.6 Machine Check Save/Restore Register 0 (MCSRR0)
MCSRR0 is an SPR that is used to save machine state on Machine Check interrupts, and to restore machine
state when an
rfmci is executed. When a machine check interrupt occurs, MCSRR0 is set to an address
associated with the process which was executing at the time. When
rfmci is executed, instruction execution
returns to the address in MCSRR0.
In general, MCSRR0 contains the address of the instruction that caused the Machine Check interrupt, or the
address of the instruction to return to after a machine check interrupt is serviced. See the individual descrip-
tions under Interrupt Definitions on page 175 for an explanation of the precise address recorded in MCSRR0
for each Machine Check interrupt type.
MCSRR0 can be written from a GPR using mtspr, and can be read into a GPR using mfspr.
6.4.7 Machine Check Save/Restore Register 1 (MCSRR1)
MCSRR1 is an SPR that is used to save machine state on Machine Check interrupts, and to restore machine
state when an
rfmci is executed. When a machine check interrupt is taken, the contents of the MSR (prior to
the MSR being cleared by the interrupt) are placed into MCSRR1. When
rfmci is executed, the MSR is
restored with the contents of MCSRR1.
Bits of MCSRR1 that correspond to reserved bits in the MSR are also reserved.
Figure 6-5. Critical Save/Restore Register 1 (CSRR1)
0:31 Copy of the MSR when a critical interrupt is taken
Figure 6-6. Machine Check Save/Restore Register 0 (MCSRR0)
0:29 Return address for machine check interrupts
30:31 Reserved
0 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 31
FE1
WE
PR DS
CE
EE
DE
FP
ME
DWE
FE0 IS
0 29 30 31