IBM PPC440X5 CPU Core, User Manual

Page: 101 / 590

User’s Manual
Preliminary PPC440x5 CPU Core
cache.fm.
September 12, 2002
Page 101 of 589
block -- 32 bytes), it takes sixteen such dcbt operations (one for each set) before the next way of the ini-
tial set will be targeted again.
7. Execute msync and then isync again, to guarantee that all of the dcbt operations have completed and
updated the corresponding victim index fields.
8. Set the NFLOOR, TFLOOR, and TCEILING values to the desired indices for the operating normal and
transient regions of the cache. Both the NFLOOR and the TFLOOR values should be set higher than the
highest locked way of the data cache; otherwise, subsequent normal and/or transient accesses could
overwrite a way containing a line which was to be locked.
9. Set each of the normal and transient victim index fields to the value of the NFLOOR and TFLOOR,
respectively.
10. Restore the cacheability of the memory pages which were used to perform the locking function to the
desired operating values, by clearing the caching-inhibited attribute of the TLB entries which were
updated in step 2.
11. Execute msync and then isync again, to cause the new TLB entry values to take effect.
The ways of the data cache whose indices are below the lower of the NFLOOR and TFLOOR values will now
be locked.