IBM PPC440X5 CPU Core, User Manual

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User’s Manual
Preliminary PPC440x5 CPU Core
cache.fm.
September 12, 2002
Page 127 of 589
the specified cache line in the data cache (assuming that a TLB entry for the referenced memory page exists
and has read permission, and that the caching inhibited storage attribute is not set). The cache line fill associ-
ated with such a guaranteed dcbt will occur regardless of any potential instruction execution-stalling circum-
stances within the DCC.
Operation of the
dcbt instruction is affected by the CCR1[FCOM] bit, which forces the dcbt to appear to miss
the cache, even if it should really be a hit. This causes two copies of the line to be established in the cache,
simulating a multi-hit parity error. See section 4.3.3.7, “Simulating Data Cache Parity Errors for Software
Testing.”
4.3.3.5 dcread Operation
The dcread instruction can be used to directly read both the tag information and a specified data word in a
specified entry of the data cache. The data word is read into the target GPR specified in the instruction
encoding, while the tag information is read into a pair of SPRs, Data Cache Debug Tag Register High
(DCDBTRH) and Data Cache Debug Tag Register Low (DCDBTRL). The tag information can subsequently
be moved into GPRs using mfspr instructions.
The execution of the dcread instruction generates the equivalent of an EA, which is then broken down
according to the size of the cache and used to select a specific data word from a specific cache line, as
shown in Table 4-4 on page -112.
The EA generated by the dcread instruction must be word-aligned (that is, EA
30:31
must be 0); otherwise, it is
a programming error and the result is undefined.
If the CCR0[CRPE] bit is set, execution of the dcread instruction also loads parity information into the
DCDBTRL. Note that the DCDBTRL[DPAR] field, unlike all the other parity fields, loads the check values of
the parity, instead of the raw parity values. That is, the DPAR field will always load with zeros unless a parity
error has occurred, or been inserted intentionally using the appropriate bits in the CCR1. This behavior is an
artifact of the hardware design of the parity checking logic.
Execution of the dcread instruction is privileged, and is intended for use for debugging purposes only.
Programming Note:
The PPC440x5 core does not support the use of the dcread instruction when the DCC is still in
the process of performing cache operations associated with previously executed instructions
(such as line fills and line flushes). Also, the PPC440x5 core does not automatically synchronize
context between a dcread instruction and the subsequent mfspr instructions that read the
results of the dcread instruction into GPRs. In order to guarantee that the dcread instruction
operates correctly, and that the mfspr instructions obtain the results of the dcread instruction, a
sequence such as the following must be used:
msync # ensure that all previous cache operations have completed
dcread regT,regA,regB # read cache information; the contents of GPR A and GPR B are
# added and the result used to specify a cache line index to be read;
# the data word is moved into GPR T and the tag information is read
# into DCDBTRH and DCDBTRL
isync # ensure dcread completes before attempting to read results
mfdcdbtrh regD # move high portion of tag into GPR D
mfdcdbtrl regE # move low portion of tag into GPR E