IBM PPC440X5 CPU Core, User Manual

Page: 103 / 590

User’s Manual
Preliminary PPC440x5 CPU Core
cache.fm.
September 12, 2002
Page 103 of 589
4.2 Instruction Cache Controller
The instruction cache controller (ICC) delivers two instructions per cycle to the instruction unit of the
PPC440x5 core. The ICC interfaces to the PLB using a 128-bit read interface, although it supports direct
attachment to 32-bit and 64-bit PLB subsystems, as well as 128-bit PLB subsystems. The ICC handles
frequency synchronization between the PPC440x5 core and the PLB, and can operate at any ratio of
n:1, n:2,
and
n:3, where n is an integer greater than the corresponding denominator.
The ICC provides a speculative prefetch mechanism which can be configured to automatically prefetch a
burst of up to three additional lines upon any fetch request which misses in the instruction cache.
Figure 4-4. Cache Locking and Transient Mechanism (Example 2)
Cache Set n
1
Way w
2
NORMAL LINES
Way T1
Way TCEILING
NORMAL/TRANSIENT LINES
Way NFLOOR
Way NFLOOR-1
TRANSIENT LINES
Way TFLOOR
Way TFLOOR-1
LOCKED LINES
Way 0
Note 1: This example illustrates partitioning of the cache
into locked, transient, and normal regions where
the transient and normal regions partially overlap.
The figure illustrates a single set, but all sets of the
cache are partitioned according to the same victim
limit values.
Note 2: w = 31 for 8KB cache, 63 for 16KB and 32KB
cache.