User’s Manual
PPC440x5 CPU Core
Preliminary
Page 212 of 589
timers.fm.
September 12, 2002
Using
mtspr to force the DEC to 0 does not cause a Decrementer exception and thus does not cause
TSR[DIS] to be set. However, if a time base clock causes a decrement from a DEC value of 1 to occur simul-
taneously with the writing of the DEC by a
mtspr instruction, then the Decrementer exception will occur,
TSR[DIS] will be set, and the DEC will be written with the value from the mtspr.
In order for software to quiesce the activity of the DEC and eliminate all DEC exceptions, the following proce-
dure should be followed:
1. Write 0 to TCR[DIE]. This prevents a Decrementer exception from causing a Decrementer interrupt.
2. Write 0 to TCR[ARE]. This disables the DEC auto-reload feature.
3. Write 0 to the DEC to halt decrementing. Although this action does not itself cause a Decrementer excep-
tion, it is possible that a decrement from a DEC value of 1 has occurred since the last time that TSR[DIS]
was cleared.
4. Write 1 to TSR[DIS] (DEC Interrupt Status bit). This clears the Decrementer exception by setting
TSR[DIS] to 0. Because the DEC is no longer decrementing (due to having been written with 0 in step 3),
no further Decrementer exceptions are possible.
7.3 Fixed Interval Timer (FIT)
The FIT provides a mechanism for causing periodic exceptions with a regular period. The FIT would typically
be used by system software to invoke a periodic system maintenance function, executed by the Fixed Interval
Timer interrupt handler.
A Fixed Interval Timer exception occurs on a 0
→
1 transition of a selected bit from the time base. Note that a
Fixed Interval Timer exception will also occur if the selected time base bit transitions from 0
→
1 due to a
mtspr instruction that writes 1 to that time base bit when its previous value was 0.
The Fixed Interval Timer Period (FP) field of the TCR selects one of four bits from the time base, as shown in
Table 7-1.
Figure 7-5. Decrementer Auto-Reload (DECAR)
0:31
Decrementer auto-reload value
Copied to DEC at next time base clock when
DEC = 1 and auto-reload is enabled
(TCR[ARE] = 1).
Table 7-1. Fixed Interval Timer Period Selection
TCR[FP]
Time Base Bit
Period
(Time Base Clocks)
Period
(400 Mhz Clock)
0b00
TBL
19
2
13
clocks
20.48
µ
s
0b01
TBL
15
2
17
clocks
327.68
µ
s
0b10
TBL
11
2
21
clocks
5.2 ms
0
31
Summary of Contents for PPC440X5 CPU Core
Page 1: ...PPC440x5 CPU Core User s Manual Preliminary SA14 2613 02 September 12 2002 Title Page...
Page 22: ...User s Manual PPC440x5 CPU Core Preliminary Page 22 of 583 ppc440x5LOT fm September 12 2002...
Page 26: ...User s Manual PPC440x5 CPU Core Preliminary Page 26 of 589 preface fm September 12 2002...
Page 38: ...User s Manual PPC440x5 CPU Core Preliminary Page 38 of 589 overview fm September 12 2002...
Page 94: ...User s Manual PPC440x5 CPU Core Preliminary Page 94 of 589 init fm September 12 2002...
Page 132: ...User s Manual PPC440x5 CPU Core Preliminary Page 132 of 589 cache fm September 12 2002...
Page 158: ...User s Manual PPC440x5 CPU Core Preliminary Page 158 of 589 mmu fm September 12 2002...
Page 218: ...User s Manual PPC440x5 CPU Core Preliminary Page 218 of 589 timers fm September 12 2002...
Page 248: ...User s Manual PPC440x5 CPU Core Preliminary Page 248 of 589 debug fm September 12 2002...
Page 458: ...User s Manual PPC440x5 CPU Core Preliminary Page 458 of 589 regsummIntro fm September 12 2002...
Page 568: ...User s Manual PPC440x5 CPU Core Preliminary Page 568 of 589 instalfa fm September 12 2002...
Page 588: ...User s Manual PPC440x5 CPU Core Preliminary Page 588 of 583 ppc440x5IX fm September 12 2002...
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