IBM PPC440X5 CPU Core, User Manual

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User’s Manual
PPC440x5 CPU Core Preliminary
Page 160 of 589
intrupts.fm.
September 12, 2002
Synchronous, precise interrupts are those that precisely indicate the address of the instruction causing the
exception that generated the interrupt; or, for certain synchronous, precise interrupt types, the address of the
immediately following instruction.
Synchronous, imprecise interrupts are those that may indicate the address of the instruction which caused
the exception that generated the interrupt, or the address of some instruction after the one which caused the
exception.
6.2.2.1 Synchronous, Precise Interrupts
When the execution or attempted execution of an instruction causes a synchronous, precise interrupt, the
following conditions exist when the associated interrupt handler begins execution:
• SRR0 (see Save/Restore Register 0 (SRR0) on page 167) or CSRR0 (see Critical Save/Restore Register
0 (CSRR0) on page 168) addresses either the instruction which caused the exception that generated the
interrupt, or the instruction immediately following this instruction. Which instruction is addressed can be
determined from a combination of the interrupt type and the setting of certain fields of the ESR (see
Exception Syndrome Register (ESR) on page 172).
• The interrupt is generated such that all instructions preceding the instruction which caused the exception
appear to have completed with respect to the executing processor. However, some storage accesses
associated with these preceding instructions may not have been performed with respect to other proces-
sors and mechanisms.
• The instruction which caused the exception may appear not to have begun execution (except for having
caused the exception), may have been partially executed, or may have completed, depending on the
interrupt type (see Partially Executed Instructions on page 164).
• Architecturally, no instruction beyond the one which caused the exception has executed.
6.2.2.2 Synchronous, Imprecise Interrupts
When the execution or attempted execution of an instruction causes a synchronous, imprecise interrupt, the
following conditions exist when the associated interrupt handler begins execution:
• SRR0 or CSRR0 addresses either the instruction which caused the exception that generated the inter-
rupt, or some instruction following this instruction.
• The interrupt is generated such that all instructions preceding the instruction addressed by SRR0 or
CSRR0 appear to have completed with respect to the executing processor.
• If the imprecise interrupt is forced by the context synchronizing mechanism, due to an instruction that
causes another exception that generates an interrupt (for example, Alignment, Data Storage), then SRR0
addresses the interrupt-forcing instruction, and the interrupt-forcing instruction may have been partially
executed (see Partially Executed Instructions on page 164).
• If the imprecise interrupt is forced by the execution synchronizing mechanism, due to executing an execu-
tion synchronizing instruction other than
msync or isync, then SRR0 or CSRR0 addresses the interrupt-
forcing instruction, and the interrupt-forcing instruction appears not to have begun execution (except for
its forcing the imprecise interrupt). If the imprecise interrupt is forced by an
msync or isync instruction,
then SRR0 or CSRR0 may address either the msync or isync instruction, or the following instruction.
• If the imprecise interrupt is not forced by either the context synchronizing mechanism or the execution
synchronizing mechanism, then the instruction addressed by SRR0 or CSRR0 may have been partially
executed (see Partially Executed Instructions on page 164).