IBM PPC440X5 CPU Core, User Manual

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User’s Manual
Preliminary PPC440x5 CPU Core
mmu.fm.
September 12, 2002
Page 155 of 589
Execute, Read and Write Access Control exceptions may be used to allow software to maintain reference
and change information for a TLB entry and for its associated memory page. The following description
explains one way in which system software can maintain such reference and change information.
The TLB entry is originally written into the TLB with its access control bits (UX, SX, UR, SR, UW, and SW) off.
The first attempt of application code to use the page will therefore cause an Access Control exception and a
corresponding Instruction or Data Storage interrupt. The interrupt handler records the reference to the TLB
entry and to the associated memory page in a software table, and then turns on the appropriate access
control bit, thereby indicating that the particular TLB entry has been referenced. An initial read from the page
is handled by only turning on the appropriate UR or SR access control bit, leaving the page “read-only”.
Subsequent read accesses to the page via that TLB entry will proceed normally.
If a write access is later attempted, a Write Access Control exception type Data Storage interrupt will occur.
The interrupt handler records the change status to the memory page in a software table, and then turns on
the appropriate UW or SW access control bit, thereby indicating that the memory page associated with the
particular TLB entry has been changed. Subsequent write accesses to the page via that TLB entry will
proceed normally.
5.11 TLB Parity Operations
The TLB is parity protected against soft errors in the TLB memory array that are caused by alpha particle
impacts.
If such errors are detected, the CPU can be configured to vector to the machine check interrupt
handler, which can restore the corrupted state of the TLB from the page tables in system memory.
The TLB is a 64-entry CAM/RAM with 40 tag bits, 41 data bits, and 8 parity bits per entry. Tag and data bits
are parity protected with four parity bits for the 40-bit tag, two parity bits for 26 bits of data (i.e. those read and
written as word 1 by the tlbre and tlbwe instructions), and two more parity bits for the remaining 15 bits of
data (i.e. word 2). The parity bits are stored in the TLB entries in fields named TPAR, PAR1, and PAR2,
respectively. See Figure 5-5 TLB Entry Word Definitions
Unlike the instruction and data cache CAM/RAMs, the TLB does not detect multiple hits due to parity errors in
the tags. The TLB is a relatively small memory array, and the reduction in Soft Error Rate (SER) provided by
adding multi-hit detection to the circuit is small, and so, not worth the expense of the feature.
TLB parity bits are set any time the TLB is updated, which is always done via a
tlbwe
instruction. TLB parity
is checked each time the TLB is searched or read, whether to re-fill the ITLB or DTLB, or as a result of a
tlbsx
or
tlbre
instruction. When executing an ITLB or DTLB refill, parity is checked for the tag and both data
words. When executing a
tlbsx
, data output is not enabled for the translation and protection outputs of the
TLB, so only the tag parity is checked. When executing a
tlbre
, parity is checked only for the word specified
in the WS field of the
tlbre
instruction. Detection of a parity error causes a machine check exception. If
MSR[ME] is set (which is the usual case), the processor takes a machine check interrupt.
5.11.1 Reading TLB Parity Bits with tlbre
If CCR0[CRPE] is set, execution of a
tlbre
instruction updates the target register with parity values as well as
the tag or other data from the TLB. However, since a
tlbre
that detects a parity error will cause a machine
check exception, the target register can only be updated with a “bad” parity value if the MSR[ME] bit is
cleared, preventing the machine check interrupt. Thus the usual flow of code that detects a parity error in the
TLB and then finds out which entry is erroneous would proceed as:
1. A tlbre instruction is executed from normal OS code, resulting in a parity exception. The exception sets
MCSR[TLBE] and MCSR[MCS].