IBM PPC440X5 CPU Core, User Manual

Page: 37 / 590

User’s Manual
Preliminary PPC440x5 CPU Core
overview.fm.
September 12, 2002
Page 37 of 589
PowerPC floating point unit (single or double precision), multimedia engine, DSP, or other custom function
implementing algorithms appropriate for specific system applications. The APU interface supports dual-issue
pipeline designs, and can be used with macros that contain their own register files, or with simpler macros
which use the CPU GPR file for source and/or target operands. APU load and store instructions can directly
access the PPC440x5 data cache, with operands of up to a quadword (16 bytes) in length.
The APU interface provides the capability for a coprocessor to execute concurrently with the PPC440x5 core
instructions that are not part of the PowerPC instruction set. Accordingly, areas have been reserved within
the architected instruction space to allow for these customer-specific or application-specific APU instruction
set extensions.
1.4.4 JTAG Port
The PPC440x5 JTAG port is enhanced to support the attachment of a debug tool such as the RISCWatch
product from IBM. Through the JTAG test access port, and using the debug facilities designed into the
PPC440x5 core, a debug workstation can single-step the processor and interrogate internal processor state
to facilitate hardware and software debugging. The enhancements comply with the IEEE 1149.1 specification
for vendor-specific extensions, and are therefore compatible with standard JTAG hardware for boundary-
scan system testing.