IBM PPC440X5 CPU Core, User Manual

Page: 141 / 590

User’s Manual
Preliminary PPC440x5 CPU Core
mmu.fm.
September 12, 2002
Page 141 of 589
The Real Page Number (RPN) and Extended Real Page Number (ERPN) fields of the matching TLB entry
provide the page number portion of the real address. Let n=32–log
2
(page size in bytes) where page size is
specified by the SIZE field of the matching TLB entry. Bits n:31 of the effective address (the “page offset”) are
appended to bits 0:n–1 of the RPN field, and bits 0:3 of the ERPN field are prepended to this value to produce
the 36-bit real address (that is, RA = ERPN
0:3
|| RPN
0:n–1
|| EA
n:31
).
Figure 5-2 illustrates the address translation process, while Table 5-3 defines the relationship between the
different page sizes and the real address formation.
32-bit Effective Address
36-bit Real Address
41-bit Virtual Address
NOTE: n = 32–log
2
(
page size
)
PID
Effective Page Number (EPN) Offset
0 n 31
Real Page Number (RPN)
Offset
n 31 0
64-entry TLB
MSR[IS] for instruction fetch
AS
MSR[DS] for data storage accesses
RPN
0:n-1
n–1
n–1
ERPN
0:3
0
7
0 3
Extended
RPN
Figure 5-2. Effective-to-Real Address Translation Flow