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IBM PPC440X5 CPU Core, User Manual

The IBM PPC440X5 CPU Core is a powerful processor designed for high-performance computing tasks. This user manual provides detailed instructions on how to maximize the capabilities of this processor. Download your free manual from manualshive.com and unlock the full potential of your device.

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User’s Manual

PPC440x5 CPU Core

Preliminary

Page 196 of 589

intrupts.fm.

September 12, 2002

specified by the various debug facility registers. This exception can occur regardless of
debug mode, and regardless of the value of MSR[DE].

Branch Taken (BRT) exception

A BRT Debug exception occurs when BRT debug events are enabled (DBCR0[BRT]=1) and
execution is attempted of a branch instruction for which the branch conditions are met. This
exception cannot occur in internal debug mode when MSR[DE]=0, unless external debug
mode or debug wait mode is also enabled.

Trap (TRAP) exception

A TRAP Debug exception occurs when TRAP debug events are enabled (DBCR0[TRAP]=1)
and execution is attempted of a tw or twi instruction that matches any of the specified trap
conditions. This exception can occur regardless of debug mode, and regardless of the value
of MSR[DE].

Return (RET) exception

A RET Debug exception occurs when RET debug events are enabled (DBCR0[RET]=1) and
execution is attempted of an rfi, rfci, or rfmci instruction. For rfi, the RET Debug exception
can occur regardless of debug mode and regardless of the value of MSR[DE]. For rfci or
rfmci

, the RET Debug exception cannot occur in internal debug mode when MSR[DE]=0,

unless external debug mode or debug wait mode is also enabled.

Instruction Complete (ICMP) exception

An ICMP Debug exception occurs when ICMP debug events are enabled (DBCR0[ICMP]=1)
and execution of any instruction is completed. This exception cannot occur in internal debug
mode when MSR[DE]=0, unless external debug mode or debug wait mode is also enabled.

Interrupt (IRPT) exception

An IRPT Debug exception occurs when IRPT debug events are enabled (DBCR0[IRPT]=1)
and an interrupt occurs. For non-critical class interrupt types, the IRPT Debug exception can
occur regardless of debug mode and regardless of the value of MSR[DE]. For critical class
interrupt types, the IRPT Debug exception cannot occur in internal debug mode (regardless
of the value of MSR[DE]), unless external debug mode or debug wait mode is also enabled.

Unconditional Debug Event (UDE) exception

A UDE Debug exception occurs when an Unconditional Debug Event is signaled over the
JTAG interface to the PPC440x5 core. This exception can occur regardless of debug mode,
and regardless of the value of MSR[DE].

There are four debug modes supported by the PPC440x5 core. They are: internal debug mode, external
debug mode, debug wait mode, and trace mode. Debug exceptions and interrupts are affected by the debug
mode(s) which are enabled at the time of the Debug exception. Debug interrupts occur only when internal
debug mode is enabled, although it is possible for external debug mode and/or debug wait mode to be
enabled as well. The remainder of this section assumes that internal debug mode is enabled and that
external debug mode and debug wait mode are not enabled, at the time of a Debug exception.

See Chapter 8, “Debug Facilities” for more information on the different debug modes and the behavior of
each of the Debug exception types when operating in each of the modes.

Summary of Contents for PPC440X5 CPU Core

Page 1: ...PPC440x5 CPU Core User s Manual Preliminary SA14 2613 02 September 12 2002 Title Page...

Page 2: ...property rights of IBM or third parties All information contained in this document was obtained in specific environments and is presented as an illustration The results obtained in other operating env...

Page 3: ...nterfaces 35 1 4 1 Processor Local Bus PLB 36 1 4 2 Device Control Register DCR Interface 36 1 4 3 Auxiliary Processor Unit APU Port 36 1 4 4 JTAG Port 37 2 Programming Model 39 2 1 Storage Addressing...

Page 4: ...Instructions 62 2 4 4 1 Cache Management Instructions 62 2 4 4 2 TLB Management Instructions 62 2 4 4 3 Storage Synchronization Instructions 63 2 4 5 Allocated Instructions 63 2 5 Branch Processing 6...

Page 5: ...bug Instruction Summary 108 4 2 4 2 Core Configuration Register 0 CCR0 108 4 2 4 3 Core Configuration Register 1 CCR1 110 4 2 4 4 icbt Operation 111 4 2 4 5 icread Operation 112 4 2 4 6 Instruction Ca...

Page 6: ...47 5 7 1 Memory Management Unit Control Register MMUCR 148 5 7 2 Process ID PID 151 5 8 Shadow TLB Arrays 151 5 9 TLB Management Instructions 152 5 9 1 TLB Search Instruction tlbsx 153 5 9 2 TLB Read...

Page 7: ...14 Data TLB Error Interrupt 193 6 5 15 Instruction TLB Error Interrupt 194 6 5 16 Debug Interrupt 195 6 6 Interrupt Ordering and Masking 199 6 6 1 Interrupt Ordering Software Requirements 199 6 6 2 In...

Page 8: ...struction Types 230 8 3 3 Data Value Compare DVC Debug Event 231 8 3 3 1 DVC Debug Event Fields 232 8 3 3 2 DVC Debug Event Processing 233 8 3 3 3 DVC Debug Events Applied to Instructions that Result...

Page 9: ...6 adde 257 addi 258 addic 259 addic 260 addis 261 addme 262 addze 263 and 264 andc 265 andi 266 andis 267 b 268 bc 269 bcctr 275 bclr 278 cmp 282 cmpi 283 cmpl 284 cmpli 285 cntlzw 286 crand 287 crand...

Page 10: ...aux 327 lhax 328 lhbrx 329 lhz 330 lhzu 331 lhzux 332 lhzx 333 lmw 334 lswi 335 lswx 337 lwarx 339 lwbrx 340 lwz 341 lwzu 342 lwzux 343 lwzx 344 macchw 345 macchws 346 macchwsu 347 macchwu 348 machhw...

Page 11: ...ulli 381 mullw 382 nand 383 neg 384 nmacchw 385 nmacchws 386 nmachhw 387 nmachhws 388 nmaclhw 389 nmaclhws 390 nor 391 or 392 orc 393 ori 394 oris 395 rfci 396 rfi 397 rfmci 398 rlwimi 399 rlwinm 400...

Page 12: ...46 wrteei 447 xor 448 xori 449 xoris 450 10 Register Summary 451 10 1 Register Categories 451 10 2 Reserved Fields 457 10 3 Device Control Registers 457 10 4 Alphabetical Register Listing 459 CCR0 460...

Page 13: ...dix A Instruction Summary 519 A 1 Instruction Formats 519 A 1 1 Instruction Fields 520 A 1 2 Instruction Format Diagrams 521 A 1 2 1 I Form 522 A 1 2 2 B Form 522 A 1 2 3 SC Form 522 A 1 2 4 D Form 52...

Page 14: ...User s Manual PPC440x5 CPU Core Preliminary Page 14 of 583 ppc440x5TOC fm September 12 2002 Index 571 Revision Log 589...

Page 15: ...1 Data Cache Normal Victim Registers DNV0 DNV3 97 Figure 4 1 Data Cache Transient Victim Registers DTV0 DTV3 97 Figure 4 2 Instruction Cache Victim Limit IVLIM 99 Figure 4 2 Data Cache Victim Limit DV...

Page 16: ...mer Control Register TCR 216 Figure 7 8 Timer Status Register TSR 217 Figure 8 1 Debug Control Register 0 DBCR0 239 Figure 8 2 Debug Control Register 1 DBCR1 240 Figure 8 3 Debug Control Register 2 DB...

Page 17: ...Cache Transient Victim Registers ITV0 ITV3 495 Figure 10 30 Instruction Cache Victim Limit IVLIM 496 Figure 10 31 Interrupt Vector Offset Registers IVOR0 IVOR15 497 Figure 10 32 Interrupt Vector Prefi...

Page 18: ...Figure A 2 B Instruction Format 522 Figure A 3 SC Instruction Format 522 Figure A 4 D Instruction Format 522 Figure A 5 X Instruction Format 523 Figure A 6 XL Instruction Format 524 Figure A 7 XFX Ins...

Page 19: ...16 System Linkage Instructions 61 Table 2 17 Processor Synchronization Instruction 62 Table 2 18 Cache Management Instructions 62 Table 2 19 TLB Management Instructions 62 Table 2 20 Storage Synchroni...

Page 20: ...bcla 270 Table 9 9 Extended Mnemonics for bcctr bcctrl 275 Table 9 10 Extended Mnemonics for bclr bclrl 279 Table 9 11 Extended Mnemonics for cmp 282 Table 9 12 Extended Mnemonics for cmpi 283 Table 9...

Page 21: ...for twi 444 Table 10 1 Register Categories 452 Table 10 2 Special Purpose Registers Sorted by SPR Number 454 Table 10 3 Interrupt Types Associated with each IVOR 497 Table A 1 PPC440x5 Instruction Sy...

Page 22: ...User s Manual PPC440x5 CPU Core Preliminary Page 22 of 583 ppc440x5LOT fm September 12 2002...

Page 23: ...re JTAG debug interface with extensive integrated debug facilities including real time trace Who Should Use This Book This book is for system hardware and software developers and for application devel...

Page 24: ...ll registers are shown as having bit numbers from 0 to 63 with bit 63 being the least significant This manual describes a 32 bit subset implementation of the architecture Architected registers are des...

Page 25: ...or in a register denotes an allocated bit in a register A shaded field denotes a field that is reserved or allocated in an instruction or in a register Related Publications The following book describ...

Page 26: ...User s Manual PPC440x5 CPU Core Preliminary Page 26 of 589 preface fm September 12 2002...

Page 27: ...s sizes optimized for 32KB The processor local bus PLB system interface has been extended to 128 bitsand is fully compatible with the IBM CoreConnect on chip system architecture providing the framewor...

Page 28: ...for transient instructions and data High associativity permits efficient allocation of cache memory Critical word first data access and forwarding Cache tags and data are parity protected against soft...

Page 29: ...PPC440x5 as a PowerPC Implementation The PPC440x5 core implements the full 32 bit fixed point subset of the Book E Enhanced PowerPC Archi tecture The PPC440x5 core fully complies with these architectu...

Page 30: ...to any combination of the three execution pipelines and or the APU interface see Execution Pipelines below and Auxiliary Processor Unit APU Port on page 36 The instruction unit includes a branch unit...

Page 31: ...ions provides detailed information on instruction timings and performance implications in the PPC440x5 core 1 3 3 Instruction and Data Cache Controllers The PPC440x5 core provides separate instruction...

Page 32: ...cache can either allocate the line in the cache by reading it in and storing the new data into the cache or alterna tively bypassing the cache on a miss and simply storing the data to memory This cha...

Page 33: ...h that at any given time the TLB can contain entries for any combination of page sizes In order for an address translation to occur a valid entry for the page containing the virtual address must be in...

Page 34: ...ed bit from the Time Base Users can select one of four intervals for the watchdog period again by setting a control field in the TCR to select the appropriate bit from the Time Base Upon the first tra...

Page 35: ...ssing architected processor resources setting hardware and software breakpoints and monitoring processor status In external debug mode debug events can architecturally freeze the processor While the p...

Page 36: ...e PLB supports Specifically each interface supports up to three pipelined request acknowledge sequences prior to performing the data transfers associ ated with the first request For the data cache if...

Page 37: ...a coprocessor to execute concurrently with the PPC440x5 core instructions that are not part of the PowerPC instruction set Accordingly areas have been reserved within the architected instruction spac...

Page 38: ...User s Manual PPC440x5 CPU Core Preliminary Page 38 of 589 overview fm September 12 2002...

Page 39: ...ddress whenever it executes a storage access branch cache management or translation lookaside buffer TLB management instruction or when it fetches the next sequential instruction 2 1 1 Storage Operand...

Page 40: ...e Access InstructionType Alignment Effects Integer load store halfword Broken into two byte accesses if crosses 16 byte boundary EA 28 31 0b1111 otherwise no effect Integer load store word Broken into...

Page 41: ...an instruction storage operand to cross any word boundary including the maximum address boundary Effective address arithmetic which calculates the starting address for storage operands wraps around f...

Page 42: ...FFF FFFC the result placed into the LR is architecturally undefined although once again the PPC440x5 core wraps the LR update value back to address 0 Again however software should not depend on this b...

Page 43: ...byte ordering is used is controlled on a memory page basis by the endian E storage attribute which is a field within the TLB entry for the page The endian storage attribute is set to 0 for a big endia...

Page 44: ...ions in a big endian program image are arranged with the most significant byte MSB of the instruction word at the lowest numbered address Consider the big endian mapping of instruction p at address 0x...

Page 45: ...Data byte ordering in memory depends upon the data type byte halfword word and so on of a specific data item It is only when moving a data item of a specific type from or to an architected register as...

Page 46: ...the next register starting with the most signif icant byte and so on are transferred to or from memory at sequentially higher numbered addresses This behavior for byte strings ensures that if two str...

Page 47: ...ories according to the processor functions with which they are asso ciated In addition each register is classified as being of a particular type as characterized by the specific instructions which are...

Page 48: ...cessing GPR0 GPR1 GPR31 GPR2 Condition Register CR XER Link Register LR CTR Timer TBL TBU SPRG4 SPRG5 SPRG7 SPRG5 Processor Control User SPR General 0 USPRG0 Figure 2 1 User Programming Model Register...

Page 49: ...gisters DBCR0 DBCR1 Data Value Compares DVC1 DVC2 Instruction Cache Debug Data Register ICDBDR Storage Control Process ID PID MMU Control Register MMUCR PIR Processor ID Register IVOR0 IVOR15 Interrup...

Page 50: ...9 DBDR Supervisor SPR 247 DBSR Supervisor SPR 244 DVC1 DVC2 Supervisor SPR 246 IAC1 IAC4 Supervisor SPR 245 Device Control Implemented outside core Supervisor DCR 53 Integer Processing GPR0 GPR31 User...

Page 51: ...r 12 2002 Page 51 of 589 Timer DEC Supervisor SPR 211 DECAR Supervisor write only SPR 211 TBL TBU User read Supervisor write SPR 209 TCR Supervisor SPR 215 TSR Supervisor SPR 216 Table 2 3 Register Ca...

Page 52: ...pdated as a side effect of the execution of various instructions For example the Integer Exception Register XER see Integer Exception Register XER on page 72 is an SPR which is updated with arithmetic...

Page 53: ...data between GPRs and the DCRs DCRs may be used to control various on chip system functions such as the operation of on chip buses peripherals and certain processor core behaviors 2 3 Instruction Clas...

Page 54: ...defined instructions which are not supported within the PPC440x5 core One is a TLB management instruction tlbiva TLB Invalidate Virtual Address that is specifically intended for coherent multiprocesso...

Page 55: ...opcode In order to ensure portability between the PPC440x5 and future PowerPC Book E implementations software should take care to only use the defined opcode for icbt and avoid usage of the previous...

Page 56: ...uction on the other hand either has no effect that is is treated as a no operation instruction or causes an Illegal Instruction exception type Program interrupt on imple mentations such as the PPC440x...

Page 57: ...Types Integer Integer Storage Access load store Integer Arithmetic add subtract multiply divide negate Integer Logical and andc or orc xor nand nor xnor extend sign count leading zeros Integer Compar...

Page 58: ...which one of the source operands is a field in the instruction Most integer arithmetic instructions have versions that can update CR CR0 and or XER SO OV Summary Overflow Overflow based on the result...

Page 59: ...nteger trap instructions in the PPC440x5 2 4 1 6 Integer Rotate Instructions These instructions rotate operands stored in the GPRs Rotate instructions can also mask rotated operands Table 2 10 lists t...

Page 60: ...truction address or an absolute address or contained in the LR or CTR See Branch Processing on page 64 for more information on branch operations Table 2 13 lists the branch instructions in the PPC440x...

Page 61: ...ructions in the PPC440x5 2 4 3 3 System Linkage Instructions These instructions invoke supervisor software level for system services and return from interrupts Table 2 16 lists the system linkage inst...

Page 62: ...e also provided to fill or invalidate instruction cache blocks Table 2 18 lists the cache management instructions in the PPC440x5 2 4 4 2 TLB Management Instructions The TLB management instructions re...

Page 63: ...of the PowerPC Book E architecture but they are included as part of the PPC440x5 core Architecturally they are considered allocated instructions as they use opcodes which are within the allocated cla...

Page 64: ...bclr branch conditional to LR and bcctr branch conditional to CTR do not use absolute nor relative addressing Instead they use indirect addressing in which the target of the branch is specified indir...

Page 65: ...n the prefetched instructions which were fetched from addresses down the wrong path of the branch must be discarded and new instructions fetched from the correct path Table 2 22 BO Field Definition BO...

Page 66: ...aken Also if the branch instruc tion is any form of bclr or bcctr except the unconditional form then s 0 and the branch is predicted not taken There is a peculiar consequence of this prediction algori...

Page 67: ...a target address for the bcctr instruction enabling indirect branching to any address Access to the CTR is non privileged 2 5 5 3 Condition Register CR The CR is used to record certain information co...

Page 68: ...ster Field 0 4 7 CR1 Condition Register Field 1 8 11 CR2 Condition Register Field 2 12 15 CR3 Condition Register Field 3 16 19 CR4 Condition Register Field 4 20 23 CR5 Condition Register Field 5 24 27...

Page 69: ...ied CR field and clears the corresponding XER bits Integer compare instructions update a specified CR field CR logical instructions update a specified CR bit with the result of any one of eight logica...

Page 70: ...s the sign of an instruction result indicated in CR CR0 might not represent the true infinitely precise algebraic result of the instruction that set CR0 For example if an add instruction adds two larg...

Page 71: ...ing Integer processing includes loading and storing data between memory and GPRs as well as performing various operations on the values in GPRs and other registers the categories of integer instructio...

Page 72: ...the fields of the XER in more detail Access to the XER is non privileged Figure 2 7 Integer Exception Register XER 0 SO Summary Overflow 0 No overflow has occurred 1 Overflow has occurred Can be set...

Page 73: ...me subsequent to the last clearing of XER SO by mtspr XER or mcrxr XER SO is read along with the rest of the XER into a GPR by mfspr XER In addition various integer instructions copy XER SO into CR CR...

Page 74: ...bit result XER CA 1 indicates a carry The integer shift right algebraic instructions update XER CA to indicate whether or not any 1 bits were shifted out of the least significant bit of the result if...

Page 75: ...of these registers is as temporary storage locations For example a routine might save the contents of a GPR to an SPRG and later restore the GPR from it This is faster than a save restore to a memory...

Page 76: ...a cache and auxiliary processor opera tion speculative instruction fetching trace and the operation of the cache block touch instructions The CCR0 is written from a GPR using mtspr and can be read int...

Page 77: ...led instructions not broadcast to APU for decoding This mechanism is provided as a means of reduc ing power consumption when an auxilliary pro cessor is not attached and or is not being used See Initi...

Page 78: ...ative Line Threshold Number of doublewords that must have already been filled in order that the current speculative line fill is not abandoned on a redirection of the instruction stream See Speculativ...

Page 79: ...n page 130 16 19 MMUPEI Memory Management Unit Parity Error Insert 0 record even parity normal 1 record odd parity simulate parity error Controls inversion of parity bits recorded for the tag field in...

Page 80: ...mode which is problem state Hence the value 1 in the field indicates problem state and not privileged as one might expect 2 8 1 Privileged Instructions The following instructions are privileged and ca...

Page 81: ...tions to perform speculative accesses to memory either for instruction fetching or for data loads A speculative access is defined as any access that is not required by the sequential execution model S...

Page 82: ...nd all exceptions that they will cause 2 All instructions preceding the operation must complete in the context in which they were initiated That is they must not be affected by any context changes cau...

Page 83: ...on Execution synchronization is a subset of context synchronization An execution synchronizing operation satisfies the first two requirements of context synchronizing operations but not the latter two...

Page 84: ...s guarantee that all preceding storage accesses have actually been performed with respect to the memory subsystem before the execution of any instruction after the msync Note that this requirement goe...

Page 85: ...on page 89 TCR WRC is set to 0 thereby disabling the Watchdog timer reset operation TSR WRS records the type of the just ended reset operation if the reset was initiated by the Watchdog Timer otherwi...

Page 86: ...d in Table 3 1 but which are not identified in the previous list as being architecturally required should be treated as undefined by the initialization software During chip initialization some chip co...

Page 87: ...vent has not occurred ESR MCI 0 Synchronous Instruction Machine Check exception has not occurred MCSR MCS 0 Asynchronous Instruction Machine Check exception has not occurred MSR WE 0 Wait state disabl...

Page 88: ...ified by core input sig nals W 0 Write through storage attribute disabled I 1 Caching inhibited storage attribute enabled M 0 Memory coherent storage attribute disabled G 1 Guarded storage attribute e...

Page 89: ...4 Initialization Software Requirements After a reset operation occurs the PPC440x5 core is initialized to a minimum configuration to enable the fetching and execution of the software initialization co...

Page 90: ...no AP attached 2 Enable disable broadcast of trace information save power if not tracing 3 Enable configure or disable speculative instruction cache line prefetching 4 Specify behavior for icbt and d...

Page 91: ...of TLB entry unless using TID 0 4 Setup for subsequent MSR IS DS initialization to correspond to TS field of TLB entry Only necessary if TS field of TLB entry being set to 1 MSR IS DS already reset to...

Page 92: ...s 2 Clear DBSR to initialize IAC auto toggle status 3 Initialize IAC1 IAC4 DAC1 DAC2 DVC1 DVC2 registers to desired values 4 Write MSR DWE to enable Debug Wait mode if desired 5 Write DBCR0 to enable...

Page 93: ...sequent Machine Check exceptions will result in a Machine Check interrupt 5 Context synchronize to establish new MSR context isync 16 Initialize any other processor core resources as required by the s...

Page 94: ...User s Manual PPC440x5 CPU Core Preliminary Page 94 of 589 init fm September 12 2002...

Page 95: ...detailed information about the operation of the instruction and data cache controllers and arrays 4 1 Cache Array Organization and Operation The instruction and data cache arrays are organized identi...

Page 96: ...ctim The way selected to be the victim for replacement is controlled by a field within a Special Purpose Register SPR There is a separate victim index field for each set within the cache The registers...

Page 97: ...g to the size of the cache and the type of access being performed the value is wrapped back to the index of the first way for that type of access The first and last ways for the different types of acc...

Page 98: ...V0 VNDXC 2 7 xxV2 VNDXC 2 7 11 xxV0 VNDXD 3 7 xxV0 VNDXD 2 7 xxV2 VNDXD 2 7 12 xxV1 VNDXA 3 7 xxV1 VNDXA 2 7 xxV3 VNDXA 2 7 13 xxV1 VNDXB 3 7 xxV1 VNDXB 2 7 xxV3 VNDXB 2 7 14 xxV1 VNDXC 3 7 xxV1 VNDXC...

Page 99: ...nstead of displacing other areas of the cache which may contain other data that should remain in the cache A set of fields in a pair of victim limit registers specifies which ways of the cache are use...

Page 100: ...NFLOOR and the TCEILING is lower than the last way of the cache In this scenario the ways between the TFLOOR and the NFLOOR contain only transient lines while the ways between the NFLOOR and the TCEI...

Page 101: ...OR values should be set higher than the highest locked way of the data cache otherwise subsequent normal and or transient accesses could overwrite a way containing a line which was to be locked 9 Set...

Page 102: ...gh some configurations are not necessarily useful or practical Figure 4 3 Cache Locking and Transient Mechanism Example 1 1 Cache Set n 1 Way w2 NORMAL LINES Way NFLOOR Way TCEILING TRANSIENT LINES Wa...

Page 103: ...esponding denominator The ICC provides a speculative prefetch mechanism which can be configured to automatically prefetch a burst of up to three additional lines upon any fetch request which misses in...

Page 104: ...ction cache If the memory page containing the line is caching inhibited the line will remain in the ICLFD until it is displaced by a subsequent request for another cache line either cachable or cachin...

Page 105: ...nt a fixed length burst request to the instruction PLB interface requesting the additional cache line s The burst request is presented after the cache line request for the initial cache line requested...

Page 106: ...to bypass instructions to the instruction unit but it will not be written into the instruction cache and it will be overwritten in the ICLFD buffer as soon as instruc tions for a new line begin arriv...

Page 107: ...ress translation architecture of PowerPC Book E is such that the low order address bits 22 31 are always the same for the EA VA and real address RA because these bits are never translated due to the m...

Page 108: ...by software to manage the instruction cache 4 2 4 2 Core Configuration Register 0 CCR0 The CCR0 register controls the speculative prefetch mechanism and the behavior of the icbt instruction The CCR0...

Page 109: ...d instructions not broadcast to APU for decoding This mechanism is provided as a means of reduc ing power consumption when an auxilliary pro cessor is not attached and or is not being used See Initial...

Page 110: ...ready been filled in order that the current speculative line fill is not abandoned on a redirection of the instruction stream See Speculative Prefetch Mechanism on page 105 Figure 4 6 Core Configurati...

Page 111: ...ecorded for the U fields in the data cache 14 DCMPEI Data Cache Modified bit Parity Error Insert 0 record even parity normal 1 record odd parity simulate parity error Controls inversion of parity bits...

Page 112: ...ug Data Register ICDBDR while the tag information is read into a pair of SPRs the Instruction Cache Debug Tag Register High ICDBTRH and Instruction Cache Debug Tag Register Low ICDBTRL From there the...

Page 113: ...ve address associated with the cache line read by icread 24 V Cache Line Valid 0 Cache line is not valid 1 Cache line is valid The valid indicator for the cache line read by icread 25 26 TPAR Tag Pari...

Page 114: ...asserted i e Machine Check interrupts are enabled the processor vectors to the Machine Check interrupt handler As is the case for any Machine Check interrupt after vectoring to the machine check handl...

Page 115: ...wait for the CCR1 context to update icbt target line address this line fills and sets odd parity for word 0 msync wait for the fill to finish mtspr CCR1 0x0 Reset CCR1 ICDPEI0 isync wait for the CCR1...

Page 116: ...n If the cache line is not found in the array a cache miss the next action depends upon the type of instruction being executed as well as the storage attributes of the memory page containing the data...

Page 117: ...re information on accessing guarded storage Programming Note It is a programming error for a load store or dcbz instruction to reference a valid cache line in the data cache if the caching inhibited s...

Page 118: ...andling of misaligned AP and floating point loads and stores The AP interface can specify that the DCC should signal an Alignment exception on any AP or floating point load or store access which is no...

Page 119: ...n allocated and is being read into a DCLFD buffer due perhaps to a previous cacheable load access then the SWOA indication is ignored and the access is treated as if it were a store with allocate Simi...

Page 120: ...plies to stores which target caching inhibited memory pages Specifically a given store to a caching inhibited page can only be gathered with previous store operations if the bytes targeted by the give...

Page 121: ...ine without also writing that same byte to memory the corresponding dirty bit for that cache line is set if CCR1 FFF is set then all four dirty bits are Table 4 5 Data Cache Behavior on Store Accesses...

Page 122: ...on to a virtual page which is marked as non write through to have caused the cache line to be marked as dirty so that a subsequent store operation to a different virtual page mapped to the same real p...

Page 123: ...st any byte address 0 10 within a quadword Only possible due to store gathering 7 byte write request any byte address 0 9 within a quadword Only possible due to store gathering 8 byte write request an...

Page 124: ...r write request has been acknowledged the read request will be presented and it is the responsibility of the PLB subsystem to ensure that the data returned for the read request reflects the value of t...

Page 125: ...data is discarded and not flushed to memory Execution of this instruction is privileged dcbst Data Cache Block Store Writes a cache block to memory if the block has been modified and leaves the block...

Page 126: ...support for cache coherency In such systems the dcbtst instruction would attempt to estab lish the block within the data cache in such a fashion that the processor would most readily be able to subse...

Page 127: ...1 must be 0 otherwise it is a programming error and the result is undefined If the CCR0 CRPE bit is set execution of the dcread instruction also loads parity information into the DCDBTRL Note that the...

Page 128: ...ead by dcread if CCR0 CRPE 1 otherwise 0 16 19 DPAR Data parity The parity check values for the data bytes in the word read by dcread if CCR0 CRPE 1 other wise 0 20 23 MPAR Modified dirty parity The p...

Page 129: ...achine Check interrupts are enabled the processor vectors to the Machine Check interrupt handler As is the case for any machine check interrupt after vectoring to the machine check handler the MCSRR0...

Page 130: ...parity is calculated for alternating bits of the tag field to guard against a single particle strike event that upsets two adjacent bits The other data bits are physically interleaved in such a way as...

Page 131: ...nables the simulation of a multi hit parity error When set it will cause an dcbt to appear to be a miss initiating a line fill even if the line is really already in the cache Thus this bit allows the...

Page 132: ...User s Manual PPC440x5 CPU Core Preliminary Page 132 of 589 cache fm September 12 2002...

Page 133: ...s mapping and flexible memory protection Translation misses and protection faults cause precise interrupts The hardware provides sufficient information to correct the fault and restart the faulting in...

Page 134: ...bit effective address space can support 4GB Accordingly the PPC440x5 sup ports eight of the sixteen page sizes from 1KB up to 256MB as mentioned above and as listed in Table 5 2 Page Size and Effectiv...

Page 135: ...tion Fields 0 0 21 EPN Effective Page Number variable size from 4 22 bits Bits 0 n 1 of the EPN field are compared to bits 0 n 1 of the effective address EA of the storage access where n 32 log2 page...

Page 136: ...0 storage attribute for the page associated with the TLB entry The function of this storage attribute is system dependent and has no effect within the PPC440x5 core 2 17 U1 User Definable Storage Attr...

Page 137: ...errupt 1 Instruction fetch and execution is permitted from this page while MSR PR 1 2 27 UW User State Write Enable 1 bit See Write Access on page 142 0 Store operations and the dcbz instruction are n...

Page 138: ...virtual address which is then compared to the virtual addresses contained in the TLB entries Note that the tlbsx instruction also forms a virtual address for software controlled search of the TLB Thi...

Page 139: ...t handlers Otherwise an Instruction TLB Error interrupt could result upon the fetch of the interrupt handler for some other interrupt type and the registers holding the state of the routine which was...

Page 140: ...n 0b0000 0b0001 0b0010 0b0011 0b0100 0b0101 0b0110 0b0111 0b1000 0b1001 0b1010 0b1011 0b1100 0b1101 0b1110 0b1111 1KB 4KB 16KB 64KB 256KB 1MB not supported 16MB not supported 256MB not supported not s...

Page 141: ...bits 0 3 of the ERPN field are prepended to this value to produce the 36 bit real address that is RA ERPN0 3 RPN0 n 1 EAn 31 Figure 5 2 illustrates the address translation process while Table 5 3 defi...

Page 142: ...ute Access Control exception type Instruction Storage interrupt is taken See Interrupts and Exceptions on page 159 for more information 5 5 2 Write Access The UW or SW bit of aTLB entry controls write...

Page 143: ...rvisor of the processor User mode MSR PR 1 Load operations including the load class cache management instructions dcbst dcbf dcbt dcbtst icbi and icbt are permitted from a page in storage while in use...

Page 144: ...cution of a storage access or cache management instruction dcbt dcbtst and icbt instructions are treated as loads with respect to access control As such they can cause Read Access Control exceptions H...

Page 145: ...s the dirty bit s will not be set See Instruction and Data Caches on page 95 for more information on the handling of accesses to write through storage 5 6 2 Caching Inhibited I If a memory page is mar...

Page 146: ...ve access to that location could result in the loss of an item of data from the input buffer if the instruction execution is interrupted and later re attempted A data access to a guarded storage locat...

Page 147: ...a control bit in the MMUCR see Memory Management Unit Control Register MMUCR on page 148 the U1 storage attribute can be used to designate whether storage accesses to the associated memory page shoul...

Page 148: ...age attribute as transient storage attribute 10 U2SWOAE U2 Store without Allocate Enable 0 Disable U2 storage attribute control of store without allocate 1 Enable U2 storage attribute control of store...

Page 149: ...bute is set See Instruction and Data Caches on page 95 for more information on cache line allocation on store misses U1 Transient Enable U1TE Field When U1TE is 1 then the U1 storage attribute is enab...

Page 150: ...t has the potential for allowing an application program to remove a locked line from the cache The locking and unlocking of cache lines is generally a supervisor mode function as the supervisor has ac...

Page 151: ...2 Process ID PID The Process ID PID is a 32 bit register although only the lower 8 bits are defined in the PPC440x5 core The 8 bit PID value is used as a portion of the virtual address for accessing s...

Page 152: ...PID to be reflected in the shadow TLB s software must ensure that a context synchronizing operation occurs prior to any attempt to use any address associated with the updated UTLB entries either the...

Page 153: ...rwise it is set to 0 When the TLB is searched using a tlbsx instruction if a matching entry is found the parity calculated for the tag is compared to the parity stored in the TPAR field A mismatch cau...

Page 154: ...d for any purpose is more likely to be maintained than a page which has never been referenced If the contents of a given memory page are to be replaced and the contents of that page have been changed...

Page 155: ...nd 8 parity bits per entry Tag and data bits are parity protected with four parity bits for the 40 bit tag two parity bits for 26 bits of data i e those read and written as word 1 by the tlbre and tlb...

Page 156: ...ind the error in the TLB and restore it from a known good copy in main memory Note A parity error on the TLB entry which maps the machine check exception handler code prevents recovery In effect one o...

Page 157: ...ptember 12 2002 Page 157 of 589 tlbwe Rs Ra 2 write some data to the TLB with bad parity isync wait for the tlbwe s to finish mtspr CCR1 Rz Reset CCR1 MMUPEI isync wait for the CCR1 context to update...

Page 158: ...User s Manual PPC440x5 CPU Core Preliminary Page 158 of 589 mmu fm September 12 2002...

Page 159: ...rocessor saves its old context Machine State Register MSR and next instruction address and begins execution at a pre determined interrupt handler address with a modified MSR Exceptions are the events...

Page 160: ...partially executed or may have completed depending on the interrupt type see Partially Executed Instructions on page 164 Architecturally no instruction beyond the one which caused the exception has ex...

Page 161: ...n this occurs the interrupt will either be synchronous and imprecise or it will be asynchronous depending on the type of Debug exception causing the interrupt In either case CSRR0 is set to the addres...

Page 162: ...of the instruction stream is changed perhaps due to a branch instruction such that the instruction at the address associated with the Machine Check exception will not be executed then the exception wi...

Page 163: ...achine Check interrupts and left unchanged by all other interrupts See Machine State Register MSR on page 165 for more detail on the definition of the MSR 5 Instruction fetching and execution resumes...

Page 164: ...s been cleared For any load some of the bytes at the addressed storage location may have been accessed if read access to that page in which bytes were accessed is permitted by the access control mecha...

Page 165: ...to the category of processor control registers 6 4 1 Machine State Register MSR The MSR is a register of its own unique type that controls important chip functions such as the enabling or disabling o...

Page 166: ...rupts are enabled 20 FE0 Floating point exception mode 0 0 If MSR FE1 0 ignore exceptions mode if MSR FE1 1 imprecise nonrecoverable mode 1 If MSR FE1 0 imprecise recoverable mode if MSR FE1 1 precise...

Page 167: ...of the precise address recorded in SRR0 for each non critical interrupt type SRR0 can be written from a GPR using mtspr and can be read into a GPR using mfspr 6 4 3 Save Restore Register 1 SRR1 SRR1...

Page 168: ...on of the precise address recorded in CSRR0 for each critical inter rupt type CSRR0 can be written from a GPR using mtspr and can be read into a GPR using mfspr 6 4 5 Critical Save Restore Register 1...

Page 169: ...erviced See the individual descrip tions under Interrupt Definitions on page 175 for an explanation of the precise address recorded in MCSRR0 for each Machine Check interrupt type MCSRR0 can be writte...

Page 170: ...ies the quadword 16 byte aligned interrupt vector offset from the base address provided by the IVPR see Interrupt Vector Prefix Register IVPR on page 171 for its respective interrupt type IVOR0 IVOR15...

Page 171: ...to be used for the particular interrupt type The IVPR can be written from a GPR using mtspr and can be read into a GPR using mfspr Figure 6 8 Interrupt Vector Offset Registers IVOR0 IVOR15 0 15 Reser...

Page 172: ...fields The ESR can be written from a GPR using mtspr and can be read into a GPR using mfspr Figure 6 9 Interrupt Vector Prefix Register IVPR 0 15 IVP Interrupt Vector Prefix 16 31 Reserved Figure 6 1...

Page 173: ...used the exception 1 Exception occurred imprecisely SRR0 contains the address of an instruction after the one which caused the exception This field is only set for a Floating Point Enabled exception t...

Page 174: ...s an implementation dependent field of the ESR and is not part of the PowerPC Book E Archi tecture This field is only defined for a Floating Point Enabled exception type Program interrupt and then onl...

Page 175: ...lush Parity Error 0 Exception not caused by DCU Flush parity error 1 Exception caused by DCU Flush parity error Set if and only If the DCU parity error was dis covered during a DCU Flush operation See...

Page 176: ...ixed Interval Timer x EE FIE IVOR12 Watchdog Timer Watchdog Timer x x CE WIE IVOR13 Data TLB Error Data TLB Miss x ST FP AP IVOR14 Instruction TLB Error Instruction TLB Miss x IVOR15 Debug Trap x x x...

Page 177: ...ne xxx yyy zzz means that any combination of ESR xxx ESR yyy and ESR zzz may be set including all or none xxx means ESR xxx will be set 5 Byte Ordering exception type Data Storage interrupts can only...

Page 178: ...king any action s that are required by the implementation in order to clear any Critical Input exception status such that the Critical Input interrupt request input signal is deasserted before reenabl...

Page 179: ...on a parity error is detected on an access to the data cache TLB Asynchronous Machine Check exception A TLB Asynchronous Machine Check exception is caused when a parity error is detected on an access...

Page 180: ...occurrred while MSR ME was disabled Machine Check Status Register MCSR The MCSR collects status for the Machine Check exceptions that are handled as asynchronous interrupts MCSR MCS is set by any Ins...

Page 181: ...ast out of the data cache and written to memory if the address of the cache line is not valid within the system implementation 6 5 3 Data Storage Interrupt A Data Storage interrupt may occur when no h...

Page 182: ...dependent on the implementation of the floating point or auxiliary pro cessor All integer load and store instructions supported by the PPC440x5 core are supported for both big endian and little endia...

Page 183: ...age For example consider a misaligned load word instruction that targets effective address 0x00000FFF and that the page containing that address is a 4KB page The load word will thus cross the page bou...

Page 184: ...le in user mode MSR PR 1 an instruction fetch attempts to access a location in storage that is not enabled for execute access in user mode that is the TLB entry associated with the memory page being a...

Page 185: ...rnal Input and Fixed Interval Timer interrupts When an External Input interrupt occurs the interrupt processing registers are updated as indicated below all registers not listed are unchanged and inst...

Page 186: ...ther write through required or caching inhibited If a stwcx instruction causes an Alignment exception and the processor does not have the reservation from a lwarx instruction then an Alignment interru...

Page 187: ...ny SPR number other than the ones listed for mtspr plus SPRG4 7 TBH and TBL a defined instruction which is not implemented within the PPC440x5 core and which is not a floating point instruction This i...

Page 188: ...am interrupt will not occur and the instruction associated with the exception will exe cute according to the definition of the floating point unit see the user s manual for the floating point unit imp...

Page 189: ...ausing the interrupt is an auxiliary processor instruction otherwise set to 0 PIE Set to 1 if a delayed form of Floating point Enabled exception type Program interrupt otherwise set to 0 The setting o...

Page 190: ...upt occurs when no higher priority exception exists an attempt is made to execute a floating point instruction which is recognized by an attached floating point unit and MSR FP 0 When a Floating Point...

Page 191: ...ion the interrupt processing registers are updated as indicated below all registers not listed are unchanged and instruction execution resumes at address IVPR IVP IVOR9 IVO 0b0000 Save Restore Registe...

Page 192: ...all registers not listed are unchanged and instruction execution resumes at address IVPR IVP IVOR11 IVO 0b0000 Save Restore Register 0 SRR0 Set to the effective address of the next instruction to be...

Page 193: ...with respect to address translation and protection and therefore use MSR DS rather than MSR IS as part of the calculated virtual address when searching the TLB to determine translation for their targe...

Page 194: ...entry does not exist for the first page then the DEAR will be set to 0x00000FFF On the other hand if a valid TLB entry does exist for the first page but not for the second then the DEAR will be set to...

Page 195: ...AC exception An IAC Debug exception occurs when execution is attempted of an instruction whose address matches the IAC conditions specified by the various debug facility registers This exception can o...

Page 196: ...n is completed This exception cannot occur in internal debug mode when MSR DE 0 unless external debug mode or debug wait mode is also enabled Interrupt IRPT exception An IRPT Debug exception occurs wh...

Page 197: ...terrupt will occur immediately if MSR DE is 1 and the interrupt processing registers will be updated as described below If MSR DE is 0 however then the exception condition remains set in the DBSR If a...

Page 198: ...If the instruction which set MSR DE was rfi rfci or rfmci then CSRR0 is set to the address to which the rfi rfci or rfmci was returning and not to the address of the instruction which was sequentially...

Page 199: ...upt from causing the state information saved in SRR0 SRR1 CSRR0 CSRR1 or MCSRR0 MCSRR1 from a previous interrupt to be overwritten and lost the PPC440x5 core performs certain functions As a first step...

Page 200: ...mplemented in the PPC440x5 core This prevents Auxiliary Processor Unavailable interrupts as well as Auxiliary Processor Enabled and Unimplemented Operation exception type Program interrupts Note that...

Page 201: ...Only one of the above types of synchronous interrupts may have an existing exception generating it at any given time This is guaranteed by the exception priority mechanism see Exception Priorities on...

Page 202: ...g exceptions This section does not define the permitted setting of multiple exceptions for which the corresponding interrupt types are disabled The generation of exceptions for which the corresponding...

Page 203: ...oating point unit is attached to the PPC440x5 core or if the particular floating point load or store instruction is not recognized by the attached floating point unit 5 Floating Point Unavailable Floa...

Page 204: ...sing is enabled is implementation dependent 8 Data TLB Error Data TLB Miss exception 9 Data Storage all exception types except Cache Locking exception 10 Alignment Alignment exception 11 Debug DAC or...

Page 205: ...eption will occur if an attached auxiliary processor recognizes the instruction but indicates that auxiliary processor instruction processing is disabled whether or not auxiliary processor instruction...

Page 206: ...ies the priority order of the exception types that may occur within the PPC440x5 core as the result of the attempted execution of a trap tw twi instruction 1 Debug IAC exception 2 Instruction TLB Erro...

Page 207: ...xception 5 Debug ICMP exception 6 7 11 Exception Priorities for Preserved Instructions The following list identifies the priority order of the exception types that may occur within the PPC440x5 core a...

Page 208: ...C440x5 core as the result of the attempted execution of all other instructions that is those not covered by one of the sections 6 7 1 through 6 7 12 This includes both defined instructions and allocat...

Page 209: ...1 Time Base The time base is a 64 bit register which increments once during each period of the source clock and provides a time reference Access to the time base is via two Special Purpose Registers...

Page 210: ...nsitions of these bits caused by software alteration of the time base have the same effect as transitions caused by normal incrementing of the time base Figure 7 2 illustrates the TBL Figure 7 3 illus...

Page 211: ...n page 159 provides more information on the handling of Decrementer interrupts The Decrementer interrupt handler software should clear TSR DIS before re enabling MSR EE in order to avoid another Decre...

Page 212: ...s the Decrementer exception by setting TSR DIS to 0 Because the DEC is no longer decrementing due to having been written with 0 in step 3 no further Decrementer exceptions are possible 7 3 Fixed Inter...

Page 213: ...to a mtspr instruction that writes 1 to that time base bit when its previous value was 0 The Watchdog Timer Period WP field of the TCR selects one of four bits from the time base as shown in Table 7 2...

Page 214: ...riod and a maximum of two full Watchdog Timer periods must expire before an enabled Watchdog Timer exception will occur If for some reason the recurring software loop is not successfully completed and...

Page 215: ...or reset occurs This is to prevent errant code from disabling the Watchdog Timer reset function The Auto Reload Enable ARE field of the TCR is also cleared to zero by processor reset This disables the...

Page 216: ...1 time base clocks 01 225 time base clocks 10 229 time base clocks 11 233 time base clocks 2 3 WRC Watchdog Timer Reset Control 00 No Watchdog Timer reset will occur 01 Core reset 10 Chip reset 11 Sys...

Page 217: ...r clock source When set to one CCR1 TCS selects an input to the CPU core as the timer clock The input is sampled by a latch clocked by the CPU clock and so cannot cycle any faster than 1 2 the frequen...

Page 218: ...User s Manual PPC440x5 CPU Core Preliminary Page 218 of 589 timers fm September 12 2002...

Page 219: ...debug task commonly used in embedded systems develop ment For all debug modes the various debug event types are enabled by the setting of corresponding fields in Debug Control Register 0 DBCR0 and upo...

Page 220: ...hile in external debug mode the debugger may need to modify MSR or TLB values to access protected memory External debug mode relies only on internal processor resources and no Debug interrupt handling...

Page 221: ...face from the PPC440x5 core The processor does not enter the stop state nor does a Debug interrupt occur 8 3 Debug Events There are several different kinds of debug events each of which is enabled by...

Page 222: ...n address is compared to the value in the corresponding IAC register and the IAC event occurs only if the comparison is an exact match Range inclusive comparison mode DBCR1 IAC12M IAC34M 0b10 In this...

Page 223: ...1US IAC2US IAC3US IAC4US are the individual IAC user supervisor fields for each of the four IAC events The IAC user supervisor fields specify what operating mode the processor must be in order for the...

Page 224: ...ce versa When the IAC range mode auto toggle field is set to 1 this automatic toggling is enabled otherwise it is disabled It is a programming error and the results of any instruction address comparis...

Page 225: ...very long series of instructions 8 3 1 2 IAC Debug Event Processing When operating in external debug mode or debug wait mode the occurrence of an IAC debug event is recorded in the corresponding bit...

Page 226: ...these instructions effectively ignores the low order five bits of the calculated data address and the entire aligned 32 byte cache block which starts at the calculated data address as modified with th...

Page 227: ...debugger can detect each of these types of access to byte address 0x00000003 When the data address matches the address bit mask mode conditions either one or both of the DAC debug event bits correspo...

Page 228: ...real address fields for the two DAC events The DAC effective real address fields specify whether the instruction address comparison should be performed using the effective virtual or real address see...

Page 229: ...d interrupt the Debug interrupt handler software may query the DBSR IDE field to determine that the Debug interrupt has occurred imprecisely When operating in trace mode the occurrence of a DAC debug...

Page 230: ...the Debug interrupt has occurred imprecisely When operating in trace mode the occurrence of a DAC debug event simply sets the corresponding DAC field of the DBSR and is indicated over the trace interf...

Page 231: ...d with respect to both storage access control and DAC debug events and thus may cause a DAC read debug event dccci dcread iccci icread The dccci and iccci instructions do not generate an address but r...

Page 232: ...byte lanes within that word are numbered 0 1 2 and 3 starting from the left most most significant byte of the word Accordingly bits 0 3 of a given DVC byte enable field correspond to bytes 0 3 of an a...

Page 233: ...nformation 8 3 3 3 DVC Debug Events Applied to Instructions that Result in Multiple Storage Accesses Certain misaligned load and store instructions are handled by making multiple independent storage a...

Page 234: ...T debug event is simply recorded in DBSR BRT and is indicated over the trace interface and instruction execution continues 8 3 5 Trap TRAP Debug Event TRAP debug events occur when TRAP debug events ar...

Page 235: ...as no Debug interrupt will occur immediately Instead instruction execution continues and a Debug interrupt will occur if and when MSR DE is set to 1 thereby enabling Debug interrupts assuming software...

Page 236: ...nd debug wait mode both disabled and regardless of the value of MSR DE an IRPT debug event can only occur due to a non critical class interrupt Critical class interrupts Machine Check Critical Input W...

Page 237: ...debug mode nor debug wait mode with Debug interrupts disabled MSR DE 0 the occurrence of a UDE debug event will set DBSR UDE along with the Imprecise Debug Event IDE field of the DBSR The Debug interr...

Page 238: ...y of software to synchronize the context of any changes to the debug facility registers Specifically when changing the contents of any of the debug facility registers software must execute an isync in...

Page 239: ...causes a processor reset to occur 4 ICMP Instruction Completion Debug Event 0 Disable instruction completion debug event 1 Enable instruction completion debug event Instruction completions do not cau...

Page 240: ...vent 14 DAC2R DAC 2 Read Debug Event 0 Disable DAC 2 read debug event 1 Enable DAC 2 read debug event 15 DAC2W DAC 2 Write Debug Event 0 Disable DAC 2 write debug event 1 Enable DAC 2 write debug even...

Page 241: ...ss IAC1 OR address IAC2 10 14 Reserved 15 IAC12AT IAC 1 2 Auto Toggle Enable 0 Disable IAC 1 2 auto toggle 1 Enable IAC 1 2 auto toggle 16 17 IAC3US IAC 3 User Supervisor 00 Both 01 Reserved 10 Superv...

Page 242: ...User s Manual PPC440x5 CPU Core Preliminary Page 242 of 589 debug fm September 12 2002 31 IAC34AT IAC3 4 Auto Toggle Enable 0 Disable IAC 3 4 auto toggle 1 Enable IAC 3 4 auto toggle...

Page 243: ...ctive Real 00 Effective MSR DS don t care 01 Reserved 10 Virtual MSR DS 0 11 Virtual MSR DS 1 8 9 DAC12M DAC 1 2 Mode 00 Exact match 01 Address bit mask 10 Range inclusive 11 Range exclusive Match if...

Page 244: ...AND OR pairs of bytes enabled by DVC2BE 0 AND 1 OR 2 AND 3 16 19 Reserved 20 23 DVC1BE DVC 1 Byte Enables 0 3 24 27 Reserved 28 31 DVC2BE DVC 2 Byte Enables 0 3 Figure 8 4 Debug Status Register DBSR 0...

Page 245: ...AC 3 Debug Event 0 Event didn t occur 1 Event occurred 11 IAC4 IAC 4 Debug Event 0 Event didn t occur 1 Event occurred 12 DAC1R DAC 1 Read Debug Event 0 Event didn t occur 1 Event occurred 13 DAC1W DA...

Page 246: ...ata Value Compare Registers DVC1 DVC2 The DVC registers specify the data values upon which DVC debug events should occur Each of the DVC registers can be written from a GPR using mtspr and can be read...

Page 247: ...8 Debug Data Register DBDR The DBDR can be used for communication between software running on the processor and debug tool hard ware and software The DBDR can be written from a GPR using mtspr and ca...

Page 248: ...User s Manual PPC440x5 CPU Core Preliminary Page 248 of 589 debug fm September 12 2002...

Page 249: ...sk Integer Shift shift left shift right shift right algebraic Integer Select select operand Branch branch branch conditional branch to link branch to count Processor Control Condition Register Logical...

Page 250: ...ions which are implemented within the PPC440x5 core are standard for IBM PowerPC 400 Series family of embedded controllers and are not unique to the PPC440x5 The allocated instructions implemented wit...

Page 251: ...chitecturally undefined Unless otherwise noted the PPC440x5 core will execute all invalid instruction forms without causing an Illegal Instruction exception 9 3 Pseudocode The pseudocode that appears...

Page 252: ...l branch is indicated by assigning a value to NIA For instructions that do not branch the NIA is CIA 4 PC Program counter REG FLD FLD A list of fields in a named register REG FLD FLD A range of fields...

Page 253: ...the instruction descriptions instruction EA An instruction operating on a data or instruction cache block associated with an EA leave Leave innermost do loop or do loop specified in a leave statement...

Page 254: ...he Condition Register CR and the Integer Exception Register XER For discussion of the CR see Condition Register CR on page 67 For discussion of the XER see Integer Exception Register XER on page 72 9...

Page 255: ...A RB The sum of the contents of register RA and the contents of register RB is placed into register RT Registers Altered RT CR CR0 if Rc contains 1 XER SO OV if OE contains 1 add RT RA RB OE 0 Rc 0 ad...

Page 256: ...the contents of register RA and register RB is placed into register RT XER CA is set to a value determined by the unsigned magnitude of the result of the add operation Registers Altered RT XER CA CR...

Page 257: ...of the contents of register RA register RB and XER CA is placed into register RT XER CA is set to a value determined by the unsigned magnitude of the result of the add operation Registers Altered RT...

Page 258: ...nto register RT Registers Altered RT Programming Note To place an immediate sign extended value into the GPR specified by RT set RA 0 addi RT RA IM 14 RT RA IM 0 6 11 16 31 Table 9 4 Extended Mnemonic...

Page 259: ...contents of the IM field sign extended to 32 bits is placed into register RT XER CA is set to a value determined by the unsigned magnitude of the result of the add operation Registers Altered RT XER...

Page 260: ...er RT XER CA is set to a value determined by the unsigned magnitude of the result of the add operation Registers Altered RT XER CA CR CR0 Programming Note addic is one of three instructions that impli...

Page 261: ...ter RT Registers Altered RT Programming Note An addi instruction stores a sign extended 16 bit value in a GPR An addis instruction followed by an ori instruction stores an arbitrary 32 bit value in a...

Page 262: ...The sum of the contents of register RA XER CA and 1 is placed into register RT XER CA is set to a value determined by the unsigned magnitude of the result of the add operation Registers Altered RT XE...

Page 263: ...the contents of register RA and XER CA is placed into register RT XER CA is set to a value determined by the unsigned magnitude of the result of the add operation Registers Altered RT XER CA CR CR0 i...

Page 264: ...nstrset fm September 12 2002 and AND RA RS RB The contents of register RS are ANDed with the contents of register RB the result is placed into register RA Registers Altered RA CR CR0 if Rc contains 1...

Page 265: ...age 265 of 589 andc AND with Complement RA RS RB The contents of register RS are ANDed with the ones complement of the contents of register RB the result is placed into register RA Registers Altered R...

Page 266: ...The contents of register RS is ANDed with the extended IM field the result is placed into register RA Registers Altered RA CR CR0 Programming Note The andi instruction can test whether any of the 16...

Page 267: ...its right The contents of register RS are ANDed with the extended IM field the result is placed into register RA Registers Altered RA CR CR0 Programming Note The andis instruction can test whether any...

Page 268: ...displacement is obtained by concatenating two 0 bits to the right of the LI field and sign extending the result to 32 bits If the AA field contains 0 the base address is the address of the branch ins...

Page 269: ...BI field is ignored The next instruction address NIA is either the effective address of the branch target or the address of the instruction after the branch depending on whether the branch is taken o...

Page 270: ...Extended mnemonic for bc 0 cr_bit target bdnzfa Extended mnemonic for bca 0 cr_bit target bdnzfl Extended mnemonic for bcl 0 cr_bit target LR CIA 4 bdnzfla Extended mnemonic for bcla 0 cr_bit target L...

Page 271: ...xtended mnemonic for bcl 10 cr_bit target LR CIA 4 bdztla Extended mnemonic for bcla 10 cr_bit target LR CIA 4 beq cr_field target Branch if equal Use CR0 if cr_field is omitted Extended mnemonic for...

Page 272: ...onic for bcl 12 4 cr_field 1 target LR bgtla Extended mnemonic for bcla 12 4 cr_field 1 target LR ble cr_field target Branch if less than or equal Use CR0 if cr_field is omitted Extended mnemonic for...

Page 273: ...l 4 4 cr_field 1 target LR CIA 4 bngla Extended mnemonic for bcla 4 4 cr_field 1 target LR CIA 4 bnl cr_field target Branch if not less than use CR0 if cr_field is omitted Extended mnemonic for bc 4 4...

Page 274: ...target bsol Extended mnemonic for bcl 12 4 cr_field 3 target LR CIA 4 bsola Extended mnemonic for bcla 12 4 cr_field 3 target LR CIA 4 bt cr_bit target Branch if CRcr_bit 1 Extended mnemonic for bc 12...

Page 275: ...of the CTR BO4 affects branch prediction a performance improvement feature See Branch Prediction on page 65 for a complete discussion Instruction execution resumes with the instruction at the NIA If...

Page 276: ...cr_field Branch if greater than to address in CTR Use CR0 if cr_field is omitted Extended mnemonic for bcctr 12 4 cr_field 1 bgtctrl Extended mnemonic for bcctrl 12 4 cr_field 1 LR CIA 4 blectr cr_fie...

Page 277: ...mnemonic for bcctrl 4 4 cr_field 3 LR CIA 4 bnuctr cr_field Branch if not unordered to address in CTR use CR0 if cr_field is omitted Extended mnemonic for bcctr 4 4 cr_field 3 bnuctrl Extended mnemoni...

Page 278: ...is compared to BO1 as part of the branch condition If BO0 contains 1 then the CR is not tested as part of the branch condition and the BI field is ignored The next instruction address NIA is either th...

Page 279: ...to address in LR Extended mnemonic for bclr 0 cr_bit bdnzflrl Extended mnemonic for bclrl 0 cr_bit LR CIA 4 bdnztlr cr_bit Decrement CTR Branch if CTR 0 AND CRcr_bit 1 to address in LR Extended mnemo...

Page 280: ...cr_field Branch if greater than to address in LR Use CR0 if cr_field is omitted Extended mnemonic for bclr 12 4 cr_field 1 bgtlrl Extended mnemonic for bclrl 12 4 cr_field 1 LR CIA 4 blelr cr_field B...

Page 281: ...ed mnemonic for bclrl 4 4 cr_field 3 LR CIA 4 bnulr cr_field Branch if not unordered to address in LR Use CR0 if cr_field is omitted Extended mnemonic for bclr 4 4 cr_field 3 bnulrl Extended mnemonic...

Page 282: ...contains 1 the contents of CR CR0 are undefined Registers Altered CR CRn where n is specified by the BF field Invalid Instruction Forms Reserved fields Programming Note PowerPC Book E architecture de...

Page 283: ...of XER SO is placed into the same CR field Registers Altered CR CRn where n is specified by the BF field Invalid Instruction Forms Reserved fields Programming Note PowerPC Book E Architecture defines...

Page 284: ...31 contains 1 the contents of CR CR0 are undefined Registers Altered CR CRn where n is specified by the BF field Invalid Instruction Forms Reserved fields Programming Notes PowerPC Book E Architecture...

Page 285: ...he value of XER SO is placed into the same CR field Registers Altered CR CRn where n is specified by the BF field Invalid Instruction Forms Reserved fields Programming Note PowerPC Book E Architecture...

Page 286: ...Word n 0 do while n 32 if RS n 1 then leave n n 1 RA n The consecutive leading 0 bits in register RS are counted the count is placed into register RA The count ranges from 0 through 32 inclusive Regis...

Page 287: ...CRBT CRBA CRBB The CR bit specified by the BA field is ANDed with the CR bit specified by the BB field the result is placed into the CR bit specified by the BT field If instruction bit 31 contains 1 t...

Page 288: ...ment CRBT CRBA CRBB The CR bit specified by the BA field is ANDed with the ones complement of the CR bit specified by the BB field the result is placed into the CR bit specified by the BT field If ins...

Page 289: ...specified by the BB field the ones complement of the result is placed into the CR bit specified by the BT field If instruction bit 31 contains 1 the contents of CR CR0 are undefined Registers Altered...

Page 290: ...CRBB The CR bit specified by the BA field is ANDed with the CR bit specified by the BB field the ones complement of the result is placed into the CR bit specified by the BT field If instruction bit 31...

Page 291: ...d by the BB field the ones complement of the result is placed into the CR bit specified by the BT field If instruction bit 31 contains 1 the contents of CR CR0 are undefined Registers Altered CRBT Inv...

Page 292: ...t specified by the BB field the result is placed into the CR bit specified by the BT field If instruction bit 31 contains 1 the contents of CR CR0 are undefined Registers Altered CRBT Invalid Instruct...

Page 293: ...CRBA CRBB The condition register CR bit specified by the BA field is ORed with the ones complement of the CR bit specified by the BB field the result is placed into the CR bit specified by the BT fiel...

Page 294: ...ified by the BB field the result is placed into the CR bit specified by the BT field If instruction bit 31 contains 1 the contents of CR CR0 are undefined Registers Altered CRBT Invalid Instruction Fo...

Page 295: ...k Allocate Preliminary PPC440x5 CPU Core User s Manual instrset fm September 12 2002 Page 295 of 589 dcba Data Cache Block Allocate dcba is treated as a no op by the PPC440x5 core dcba RA RB 31 RA RB...

Page 296: ...invalid in the data cache The operation is performed whether or not the memory page referenced by the EA is marked as cacheable If the data block at the EA is not in the data cache no operation is pe...

Page 297: ...as cacheable If modified data existed in the data block prior to the operation of this instruction that data is lost If the data block at the EA is not in the data cache no operation is performed If i...

Page 298: ...t the EA is in the data cache and is not marked as modified or if the data block at the EA is not in the data cache no operation is performed The operation specified by this instruction is performed w...

Page 299: ...lowed to cause Data Storage interrupts nor Data TLB Error interrupts If execution of the instruction causes either of these types of exception then no operation is performed and no interrupt occurs If...

Page 300: ...egisters Altered None Invalid Instruction Forms Reserved fields Programming Notes The dcbtst instruction allows a program to begin a cache block fetch from main storage before the program needs the da...

Page 301: ...Preliminary PPC440x5 CPU Core User s Manual instrset fm September 12 2002 Page 301 of 589 This instruction is considered a load with respect to data address compare DAC Debug exceptions See Debug Int...

Page 302: ...ction bit 31 contains 1 the contents of CR CR0 are undefined Registers Altered None Invalid Instruction Forms Reserved fields Programming Notes Because dcbz can establish an address in the data cache...

Page 303: ...liminary PPC440x5 CPU Core User s Manual instrset fm September 12 2002 Page 303 of 589 This instruction is considered a store with respect to data address compare DAC Debug exceptions See Debug Interr...

Page 304: ...The instruction form including the specification of RA and RB operands is maintained for software and tool compatibility Registers Altered None Invalid Instruction Forms Reserved fields Programming N...

Page 305: ...currently contained within the cache If instruction bit 31 contains 1 the contents of CR CR0 are undefined dcread RT RA RB 31 RT RA RB 486 0 6 11 16 21 31 Register bit s Tag Field Name DCDBTRH 0 23 TR...

Page 306: ...into GPRs In order to guarantee that the dcread instruction operates correctly and that the mfspr instructions obtain the results of the dcread instruction a sequence such as the following must be use...

Page 307: ...perform 0x8000 0000 1 or n 0 the contents of register RT are undefined if the Rc field also contains 1 the contents of CR CR0 0 2 are undefined Either invalid division operation sets XER OV SO and CR...

Page 308: ...ter RT are undefined if the Rc also contains 1 the contents of CR CR0 0 2 are also undefined The invalid division operation also sets XER OV SO and CR CR0 3 if Rc contains 1 to 1 if the OE field conta...

Page 309: ...byte is found its byte number is placed into XER TBC and register RA Otherwise the number 8 is placed into XER TBC and register RA If the Rc field contains 1 XER SO is copied to CR CR0 3 and CR CR0 0...

Page 310: ...eptember 12 2002 eqv Equivalent RA RS RB The contents of register RS are XORed with the contents of register RB the ones complement of the result is placed into register RA Registers Altered RA CR CR0...

Page 311: ...RS 24 31 The least significant byte of register RS is sign extended to 32 bits by replicating bit 24 of the register into bits 0 through 23 of the result The result is placed into register RA Register...

Page 312: ...S RS 16 31 The least significant halfword of register RS is sign extended to 32 bits by replicating bit 16 of the register into bits 0 through 15 of the result The result is placed into register RA Re...

Page 313: ...MSR DS not MSR IS as part of the virtual address Also the instruction cache on the PPC440x5 is virtually tagged which means that the EA is converted to a virtual address VA and the VA is compared agai...

Page 314: ...is performed and no interrupt occurs If instruction bit 31 contains 1 the contents of CR CR0 are undefined Registers Altered None Invalid Instruction Forms Reserved fields Programming Notes This inst...

Page 315: ...02 Page 315 of 589 This instruction is considered a load with respect to Data Storage exceptions See Data Storage Interrupt on page 181 for more information This instruction is considered a load with...

Page 316: ...lidated The instruction form including the specification of RA and RB operands is maintained for software and tool compatibility Registers Altered None Invalid Instruction Forms Reserved fields Progra...

Page 317: ...g field contains the virtual address which consists of the TEA TS and TID fields See Memory Management on page 133 for more information on the function of the TS TD and TID fields This instruction can...

Page 318: ...mfspr instructions obtain the results of the icread instruction a sequence such as the following must be used icread regA regB read cache information the contents of GPR A and GPR B are added and the...

Page 319: ...Immediate if CR CRb 1 then RT RA 0 else RT RB If CR CRb 0 register RT is written with the contents of register RB If CR CRb 1 and RA 0 register RT is written with the contents of register RA If CR CRb...

Page 320: ...ync causes any caching inhibited instruction fetches from memory to be aborted and any data associated with them to be discarded Cacheable instruction fetches from memory are not aborted however as th...

Page 321: ...formed by adding a displacement to a base address The displacement is obtained by sign extending the 16 bit D field to 32 bits The base address is 0 if the RA field is 0 and is the contents of regist...

Page 322: ...isplacement to a base address The displacement is obtained by sign extending the 16 bit D field to 32 bits The base address is 0 if the RA field is 0 and is the contents of register RA otherwise The E...

Page 323: ...ess The index is the contents of register RB The base address is 0 if the RA field is 0 and is the contents of register RA otherwise The EA is placed into register RA The byte at the EA is extended to...

Page 324: ...base address The index is the contents of register RB The base address is 0 if the RA field is 0 and is the contents of register RA otherwise The byte at the EA is extended to 32 bits by concatenating...

Page 325: ...An effective address EA is formed by adding a displacement to a base address The displacement is obtained by sign extending the 16 bit D field to 32 bits The base address is 0 if the RA field is 0 and...

Page 326: ...is formed by adding a displacement to a base address The displacement is obtained by sign extending the 16 bit D field to 32 bits The base address is 0 when the RA field is 0 and is the contents of r...

Page 327: ...g an index to a base address The index is the contents of register RB The base address is 0 if the RA field is 0 and is the contents of register RA otherwise The EA is placed into register RA The half...

Page 328: ...by adding an index to a base address The index is the contents of register RB The base address is 0 if the RA field is 0 and is the contents of register RA otherwise The halfword at the EA is sign ex...

Page 329: ...lt byte ordering for the memory page referenced by the EA The resulting halfword is extended to 32 bits by concatenating 16 0 bits to its left The result is placed into register RT If instruction bit...

Page 330: ...is formed by adding a displacement to a base address The displacement is obtained by sign extending the 16 bit D field to 32 bits The base address is 0 if the RA field is 0 and is the contents of reg...

Page 331: ...displacement to a base address The displacement is obtained by sign extending the 16 bit D field to 32 bits The base address is 0 if the RA field is 0 and is the contents of register RA otherwise The...

Page 332: ...dress The index is the contents of register RB The base address is 0 if the RA field is 0 and is the contents of register RA otherwise The EA is placed into register RA The halfword at the EA is exten...

Page 333: ...base address The index is the contents of register RB The base address is 0 if the RA field is 0 and is the contents of register RA otherwise The halfword at the EA is extended to 32 bits by concaten...

Page 334: ...gh GPR 31 Invalid Instruction Forms RA is in the range of registers to be loaded including the case RA RT 0 Programming Note This instruction can be restarted meaning that it could be interrupted afte...

Page 335: ...NT 32 Otherwise the byte count is CNT NB A series of CNT consecutive bytes in main storage starting at the EA are loaded into CEIL CNT 4 consecu tive GPRs four bytes per GPR until the byte count is ex...

Page 336: ...cuted from the beginning after returning from the interrupt in which case the registers which had already been loaded prior to the interrupt will be loaded a second time Note that if RA is in the rang...

Page 337: ...g at the EA are loaded into CEIL CNT 4 consecu tive GPRs four bytes per GPR until the byte count is exhausted Bytes are loaded into GPRs the byte having the lowest address is loaded into the most sign...

Page 338: ...A or RB is in the range of registers to be loaded an invalid form see above and is also one of the regis ters which is loaded prior to the interrupt then when the instruction is restarted the re calcu...

Page 339: ...can set the reservation bit to 1 stwcx sets the reservation bit to 0 upon its completion whether or not stwcx actually stored RS to memory CR CR0 2 must be examined to determine whether RS was sent to...

Page 340: ...EA is byte reversed from the default byte ordering for the memory page referenced by the EA The result is placed into register RT If instruction bit 31 contains 1 the contents of CR CR0 are undefined...

Page 341: ...MS EA 4 An effective address EA is formed by adding a displacement to a base address The displacement is obtained by sign extending the 16 bit D field to 32 bits The base address is 0 if the RA field...

Page 342: ...address EA is formed by adding a displacement to a base address The displacement is obtained by sign extending the 16 bit D field to 32 bits The base address is 0 if the RA field is 0 and is the conte...

Page 343: ...d by adding an index to a base address The index is the contents of register RB The base address is 0 if the RA field is 0 and is the contents of register RA otherwise The EA is placed into register R...

Page 344: ...is formed by adding an index to a base address The index is the contents of register RB The base address is 0 if the RA field is 0 and is the contents of register RA otherwise The word at the EA is pl...

Page 345: ...ord of RB The signed product is summed with the contents of RT and RT is updated with the low order 32 bits of the signed sum Registers Altered RT CR CR0 if Rc contains 1 XER SO OV if OE contains 1 Ar...

Page 346: ...rder 32 bits of the signed sum If the signed sum cannot be represented in 32 bits then RT is updated with a value which is saturated to the nearest representable value That is if the signed sum is les...

Page 347: ...presented in 32 bits then RT is updated with the low order 32 bits of the unsigned sum If the unsigned sum cannot be represented in 32 bits then RT is updated with a value which is saturated to the ma...

Page 348: ...ord of RB The unsigned product is summed with the contents of RT and RT is updated with the low order 32 bits of the unsigned sum Registers Altered RT CR CR0 if Rc contains 1 XER SO OV if OE contains...

Page 349: ...ord of RB The signed product is summed with the contents of RT and RT is updated with the low order 32 bits of the signed sum Registers Altered RT CR CR0 if Rc contains 1 XER SO OV if OE contains 1 Ar...

Page 350: ...der 32 bits of the signed sum If the signed sum cannot be represented in 32 bits then RT is updated with a value which is saturated to the nearest representable value That is if the signed sum is less...

Page 351: ...resented in 32 bits then RT is updated with the low order 32 bits of the unsigned sum If the unsigned sum cannot be represented in 32 bits then RT is updated with a value which is saturated to the max...

Page 352: ...ord of RB The unsigned product is summed with the contents of RT and RT is updated with the low order 32 bits of the unsigned sum Registers Altered RT CR CR0 if Rc contains 1 XER SO OV if OE contains...

Page 353: ...d of RB The signed product is summed with the contents of RT and RT is updated with the low order 32 bits of the signed sum Registers Altered RT CR CR0 if Rc contains 1 XER SO OV if OE contains 1 Arch...

Page 354: ...er 32 bits of the signed sum If the signed sum cannot be represented in 32 bits then RT is updated with a value which is saturated to the nearest representable value That is if the signed sum is less...

Page 355: ...esented in 32 bits then RT is updated with the low order 32 bits of the unsigned sum If the unsigned sum cannot be represented in 32 bits then RT is updated with a value which is saturated to the maxi...

Page 356: ...d of RB The unsigned product is summed with the contents of RT and RT is updated with the low order 32 bits of the unsigned sum Registers Altered RT CR CR0 if Rc contains 1 XER SO OV if OE contains 1...

Page 357: ...ll storage accesses initiated by instructions executed prior to the msync have completed before any instructions after the msync begin execution However the PPC440x5 core implements the mbar instructi...

Page 358: ...002 mcrf Move Condition Register Field m BFA n BF CR CRn CR CRm The contents of the CR field specified by the BFA field are placed into the CR field specified by the BF field Registers Altered CR CRn...

Page 359: ...er from XER n BF CR CRn XER0 3 XER0 3 40 The contents of XER0 3 are placed into the CR field specified by the BF field XER0 3 are then set to 0 If instruction bit 31 contains 1 the contents of CR CR0...

Page 360: ...589 instrset fm September 12 2002 mfcr Move From Condition Register RT CR The contents of the CR are placed into register RT If instruction bit 31 contains 1 the contents of CR CR0 are undefined Regi...

Page 361: ...lid Instruction Forms Reserved fields Programming Notes Execution of this instruction is privileged The DCR number DCRN specified in the assembler language coding of the mfdcr instruction refers to a...

Page 362: ...02 mfmsr Move From Machine State Register RT MSR The contents of the MSR are placed into register RT If instruction bit 31 contains 1 the contents of CR CR0 are undefined Registers Altered RT Invalid...

Page 363: ...and corresponding SPRN values If instruction bit 31 contains 1 the contents of CR CR0 are undefined Registers Altered RT Invalid Instruction Forms Reserved fields Invalid SPRF values Programming Note...

Page 364: ...r2 mfdbdr mfdbsr mfdcdbtrh mfdcdbtrl mfdear mfdec mfdnv0 mfdnv1 mfdnv2 mfdnv3 mfdtv0 mfdtv1 mfdtv2 mfdtv3 mfdvc1 mfdvc2 mfdvlim mfesr mfiac1 mfiac2 mfiac3 mfiac4 mficdbdr mficdbtrh mficdbtrl mfinv0 mf...

Page 365: ...ivor6 mfivor7 mfivor8 mfivor9 mfivor10 mfivor11 mfivor12 mfivor13 mfivor14 mfivor15 mfivpr mflr mfmcsr mfmcsrr0 mfmcsrr1 mfmmucr mfpid mfpir mfpvr mfsprg0 mfsprg1 mfsprg2 mfsprg3 mfsprg4 mfsprg5 mfspr...

Page 366: ...uctions which were executed prior to mbar have actually completed their storage accesses However the PPC440x5 core implements the mbar instruction identically to the msync instruction and thus both ar...

Page 367: ...RS into the corresponding bits in the CR The correspondence between the bits in the FXM field and the bit copying operation is shown in the following table If instruction bit 31 contains 1 the content...

Page 368: ...valid Instruction Forms Reserved fields Programming Note Execution of this instruction is privileged The DCR number DCRN specified in the assembler language coding of the mtdcr instruction refers to a...

Page 369: ...Register MSR RS The contents of register RS are placed into the MSR If instruction bit 31 contains 1 the contents of CR CR0 are undefined Registers Altered MSR Invalid Instruction Forms Reserved field...

Page 370: ...g SPRN values If instruction bit 31 contains 1 the contents of CR CR0 are undefined Registers Altered SPR SPRN Invalid Instruction Forms Reserved fields Invalid SPRF values Programming Note Execution...

Page 371: ...mtdbcr0 mtdbcr1 mtdbcr2 mtdbdr mtdbsr mtdear mtdec mtdecar mtdnv0 mtdnv1 mtdnv2 mtdnv3 mtdtv0 mtdtv1 mtdtv2 mtdtv3 mtdvc1 mtdvc2 mtdvlim mtesr mtiac1 mtiac2 mtiac3 mtiac4 mtinv0 mtinv1 mtinv2 mtinv3 m...

Page 372: ...r5 mtivor6 mtivor7 mtivor8 mtivor9 mtivor10 mtivor11 mtivor12 mtivor13 mtivor14 mtivor15 mtivpr mtlr mtmcsr mtmcsrr0 mtmcsrr1 mtmmucr mtpid mtsprg0 mtsprg1 mtsprg2 mtsprg3 mtsprg4 mtsprg5 mtsprg6 mtsp...

Page 373: ...by the high order halfword of RB considering both source oper ands as signed integers The 32 bit result is placed into register RT Registers Altered RT CR CR0 if Rc contains 1 Architecture Note This i...

Page 374: ...d by the high order halfword of RB considering both source oper ands as unsigned integers The 32 bit result is placed into register RT Registers Altered RT CR CR0 if Rc contains 1 Architecture Note Th...

Page 375: ...y the high order halfword of RB considering both source oper ands as signed integers The 32 bit result is placed into register RT Registers Altered RT CR CR0 if Rc contains 1 Architecture Note This in...

Page 376: ...d by the high order halfword of RB considering both source oper ands as unsigned integers The 32 bit result is placed into register RT Registers Altered RT CR CR0 if Rc contains 1 Architecture Note Th...

Page 377: ...R0 if Rc contains 1 Programming Note The most significant 32 bits of the product unlike the least significant 32 bits may differ depending on whether the registers RA and RB are interpreted as signed...

Page 378: ...Rc contains 1 Programming Note The most significant 32 bits of the product unlike the least significant 32 bits may differ depending on whether the registers RA and RB are interpreted as signed or un...

Page 379: ...by the low order halfword of RB considering both source operands as signed integers The 32 bit result is placed into register RT Registers Altered RT CR CR0 if Rc contains 1 Architecture Note This ins...

Page 380: ...d by the low order halfword of RB considering both source operands as unsigned integers The 32 bit result is placed into register RT Registers Altered RT CR CR0 if Rc contains 1 Architecture Note This...

Page 381: ...47 The 48 bit product of register RA and the 16 bit IM field is formed The least significant 32 bits of the product are placed into register RT Registers Altered RT Programming Note The least signifi...

Page 382: ...OE 1 XER SO OV are set to 1 Registers Altered RT CR CR0 if Rc contains 1 XER SO OV if OE 1 Programming Note The least significant 32 bits of the product are correct regardless of whether register RA...

Page 383: ...Page 383 of 589 nand NAND RA RS RB The contents of register RS is ANDed with the contents of register RB the ones complement of the result is placed into register RA Registers Altered RA CR CR0 if Rc...

Page 384: ...RT RA 1 The twos complement of the contents of register RA are placed into register RT Registers Altered RT CR CR0 if Rc contains 1 XER SO OV if OE 1 Invalid Instruction Forms Reserved fields neg RT R...

Page 385: ...der halfword of RB The signed product is subtracted from the contents of RT and RT is updated with the low order 32 bits of the result Registers Altered RT CR CR0 if Rc contains 1 XER SO OV if OE cont...

Page 386: ...ted with the low order 32 bits of the result If the result of the subtraction cannot be represented in 32 bits then RT is updated with a value which is saturated to the nearest representable value Tha...

Page 387: ...der halfword of RB The signed product is subtracted from the contents of RT and RT is updated with the low order 32 bits of the result Registers Altered RT CR CR0 if Rc contains 1 XER SO OV if OE cont...

Page 388: ...ed with the low order 32 bits of the result If the result of the subtraction cannot be represented in 32 bits then RT is updated with a value which is saturated to the nearest representable value That...

Page 389: ...r halfword of RB The signed product is subtracted from the contents of RT and RT is updated with the low order 32 bits of the result Registers Altered RT CR CR0 if Rc contains 1 XER SO OV if OE contai...

Page 390: ...ed with the low order 32 bits of the result If the result of the subtraction cannot be represented in 32 bits then RT is updated with a value which is saturated to the nearest representable value That...

Page 391: ...he ones complement of the result is placed into register RA Registers Altered RA CR CR0 if Rc contains 1 nor RA RS RB Rc 0 nor RA RS RB Rc 1 31 RT RA RB 124 Rc 0 6 11 16 21 31 Table 9 23 Extended Mnem...

Page 392: ...of register RB the result is placed into register RA Registers Altered RA CR CR0 if Rc contains 1 or RA RS RB Rc 0 or RA RS RB Rc 1 31 RS RA RB 444 Rc 0 6 11 16 21 31 Table 9 24 Extended Mnemonics for...

Page 393: ...2 Page 393 of 589 orc OR with Complement RA RS RB The contents of register RS is ORed with the ones complement of the contents of register RB the result is placed into register RA Registers Altered RA...

Page 394: ...bits by concatenating 16 0 bits on the left Register RS is ORed with the extended IM field the result is placed into register RA Registers Altered RA ori RA RS IM 24 RS RA IM 0 6 11 16 31 Table 9 25...

Page 395: ...r 12 2002 Page 395 of 589 oris OR Immediate Shifted RA RS IM 16 0 The IM Field is extended to 32 bits by concatenating 16 0 bits on the right Register RS is ORed with the extended IM field and the res...

Page 396: ...ion is used to return from a critical interrupt The program counter PC is restored with the contents of CSRR0 and the MSR is restored with the contents of CSRR1 Instruction execution returns to the ad...

Page 397: ...critical interrupt The program counter PC is restored with the contents of SRR0 and the MSR is restored with the contents of SRR1 Instruction execution returns to the address contained in the PC Regis...

Page 398: ...ion is used to return from a machine check interrupt The program counter PC is restored with the contents of MCSRR0 and the MSR is restored with the contents of MCSRR1 Instruction execution returns to...

Page 399: ...of the mask wraps from the highest bit position back around to the lowest The rotated data is inserted into register RA in positions corresponding to the bit positions in the mask that contain a 1 bi...

Page 400: ...1 bits portion of the mask wraps from the highest bit position back around to the lowest The rotated data is ANDed with the generated mask the result is placed into register RA Registers Altered RA C...

Page 401: ...ate n 0 RA 32 n 31 RS b b n 1 RA 0 31 n 32 n0 Extended mnemonic for rlwinm RA RS b n 32 n 31 extrwi Extended mnemonic for rlwinm RA RS b n 32 n 31 CR CR0 rotlwi RA RS n Rotate left immediate RA ROTL R...

Page 402: ...instrset fm September 12 2002 srwi RA RS n Shift right immediate n 32 RA n 31 RS 0 31 n RA 0 n 1 n0 Extended mnemonic for rlwinm RA RS 32 n n 31 srwi Extended mnemonic for rlwinm RA RS 32 n n 31 CR C...

Page 403: ...e ME field with 0 bits elsewhere If the starting point of the mask is at a higher bit position than the ending point the ones portion of the mask wraps from the highest bit position back to the lowest...

Page 404: ...sc instruction is placed into SRR0 The program counter PC is then loaded with the interrupt vector address The interrupt vector address is formed by concatenating the high halfword of the Interrupt V...

Page 405: ...ber of bits specified by the contents of register RB26 31 Bits shifted left out of the most significant bit are lost and 0 bits fill vacated bit positions on the right The result is placed into regist...

Page 406: ...least significant bit are lost Bit 0 of Register RS is replicated to fill the vacated positions on the left The result is placed into register RA If register RS contains a negative number and any 1 bi...

Page 407: ...by the number of bits specified in the SH field Bits shifted out of the least significant bit are lost Bit RS0 is replicated to fill the vacated positions on the left The result is placed into regist...

Page 408: ...mber of bits specified the contents of register RB26 31 Bits shifted right out of the least significant bit are lost and 0 bits fill the vacated bit positions on the left The result is placed into reg...

Page 409: ...address EA is formed by adding a displacement to a base address The displacement is obtained by sign extending the 16 bit D field to 32 bits The base address is 0 when the RA field is 0 and is the con...

Page 410: ...rmed by adding a displacement to a base address The displacement is obtained by sign extending the 16 bit D field to 32 bits The base address is 0 when the RA field is 0 and is the contents of registe...

Page 411: ...dex to a base address The index is the contents of register RB The base address is 0 when the RA field is 0 and is the contents of register RA otherwise The least significant byte of register RS is st...

Page 412: ...index to a base address The index is the contents of register RB The base address is 0 when the RA field is 0 and is the contents of register RA otherwise The least significant byte of register RS is...

Page 413: ...EA is formed by adding a displacement to a base address The displacement is obtained by sign extending the 16 bit D field to 32 bits The base address is 0 when the RA field is 0 and is the contents of...

Page 414: ...halfword of register RS is byte reversed from the default byte ordering for the memory page referenced by the EA The resulting halfword is stored at the EA If instruction bit 31 contains 1 the content...

Page 415: ...rmed by adding a displacement to a base address The displacement is obtained by sign extending the 16 bit D field to 32 bits The base address is 0 when the RA field is 0 and is the contents of registe...

Page 416: ...dex to a base address The index is the contents of register RB The base address is 0 when the RA field is 0 and is the contents of register RA otherwise The least significant halfword of register RS i...

Page 417: ...index to a base address The index is the contents of register RB The base address is 0 when the RA field is 0 and is the contents of register RA otherwise The least significant halfword of register R...

Page 418: ...nd is the contents of register RA otherwise The contents of a series of consecutive registers starting with register RS and continuing through GPR 31 are stored into consecutive words starting at the...

Page 419: ...count is determined by the NB field If the NB field contains 0 the byte count is 32 otherwise the byte count is the contents of the NB field The contents of a series of consecutive GPRs starting with...

Page 420: ...ming Note This instruction can be restarted meaning that it could be interrupted after having already stored some of the register values to memory and then re executed from the beginning after returni...

Page 421: ...e EA The bytes in each GPR are accessed starting with the most significant byte The byte count determines the number of transferred bytes If instruction bit 31 contains 1 the contents of CR CR0 are un...

Page 422: ...effective address EA is formed by adding a displacement to a base address The displacement is obtained by sign extending the 16 bit D field to 32 bits The base address is 0 when the RA field is 0 and...

Page 423: ...gister RS is byte reversed from the default byte ordering for the memory page referenced by the EA The resulting word is stored at the EA If instruction bit 31 contains 1 the contents of CR CR0 are un...

Page 424: ...s shown in the following example to create the effect of an atomic operation to a memory area used as a semaphore between multiple processes Only lwarx can set the reservation bit to 1 stwcx sets the...

Page 425: ...DAC and or DVC exception type interrupts do not occur when the reservation bit is off at the time of execution of the stwcx Instead the stwcx instruction completes without causing the inter rupt and...

Page 426: ...formed by adding a displacement to a base address The displacement is obtained by sign extending the 16 bit D field to 32 bits The base address is 0 when the RA field is 0 and is the contents of regi...

Page 427: ...index to a base address The index is the contents of register RB The base address is 0 when the RA field is 0 and is the contents of register RA otherwise The contents of register RS are stored into...

Page 428: ...an index to a base address The index is the contents of register RB The base address is 0 when the RA field is 0 and is the contents of register RA otherwise The contents of register RS are stored in...

Page 429: ...ontains 1 subf RT RA RB OE 0 Rc 0 subf RT RA RB OE 0 Rc 1 subfo RT RA RB OE 1 Rc 0 subfo RT RA RB OE 1 Rc 1 31 RT RA RB OE 40 Rc 0 6 11 16 21 22 31 Table 9 29 Extended Mnemonics for subf subf subfo su...

Page 430: ...sters Altered RT XER CA CR CR0 if Rc contains 1 XER SO OV if OE contains 1 subfc RT RA RB OE 0 Rc 0 subfc RT RA RB OE 0 Rc 1 subfco RT RA RB OE 1 Rc 0 subfco RT RA RB OE 1 Rc 1 31 RT RA RB OE 8 Rc 0 6...

Page 431: ...sum of the ones complement of register RA register RB and XER CA is placed into register RT XER CA is set to a value determined by the unsigned magnitude of the result of the subtract operation Regist...

Page 432: ...te Carrying RT RA EXTS IM 1 if RA EXTS IM 1 232 1 then XER CA 1 else XER CA 0 The sum of the ones complement of RA the IM field sign extended to 32 bits and 1 is placed into register RT XER CA is set...

Page 433: ...The sum of the ones complement of register RA 1 and XER CA is placed into register RT XER CA is set to a value determined by the unsigned magnitude of the result of the subtract operation Registers A...

Page 434: ...the ones complement of register RA and XER CA is stored into register RT XER CA is set to a value determined by the unsigned magnitude of the result of the subtract operation Registers Altered RT XER...

Page 435: ...entry are placed into register RT and also MMUCR STID if WS 0 The parity bits in the TLB entry TPAR PAR1 and PAR2 are placed into the register RT if and only if the Cache Read Parity Enable bit CCR0...

Page 436: ...eld between a tlbre instruction which updates the field and a tlbsx instruction which uses it as a source operand There fore software must execute an isync instruction between the execution of a tlbre...

Page 437: ...found the contents of RT are undefined The record bit Rc specifies whether the results of the search will affect CR CR0 as shown above such that CR CR0 2 can be tested if there is a possibility that t...

Page 438: ...does not support coherent multi processing this instruction performs no operation and is provided only to facilitate code portability If instruction bit 31 contains 1 the contents of CR CR0 are undefi...

Page 439: ...S 0 1 or 2 respectively is ignored by tlbwe the parity is calculated from the other data bits being written to the TLB entry The contents of RA are used as an index into the TLB If this value is great...

Page 440: ...ared to indicate the type of exception causing the Program interrupt The program counter PC is then loaded with the interrupt vector address The interrupt vector address is formed by concatenating the...

Page 441: ...ed mnemonic for tw 12 RA RB twgt RA RB Trap if RA greater than RB Extended mnemonic for tw 8 RA RB twle RA RB Trap if RA less than or equal to RB Extended mnemonic for tw 20 RA RB twlge RA RB Trap if...

Page 442: ...strset fm September 12 2002 twng RA RB Trap if RA not greater than RB Extended mnemonic for tw 20 RA RB twnl RA RB Trap if RA not less than RB Extended mnemonic for tw 12 RA RB Table 9 31 Extended Mne...

Page 443: ...o 1 and the other bits ESR bits cleared to indicate the type of exception causing the Program interrupt The program counter PC is then loaded with the interrupt vector address The interrupt vector add...

Page 444: ...twi 8 RA IM twlei RA IM Trap if RA less than or equal to EXTS IM Extended mnemonic for twi 20 RA IM twlgei RA IM Trap if RA logically greater than or equal to EXTS IM Extended mnemonic for twi 5 RA I...

Page 445: ...PU Core User s Manual instrset fm September 12 2002 Page 445 of 589 twnli RA IM Trap if RA not less than EXTS IM Extended mnemonic for twi 12 RA IM Table 9 32 Extended Mnemonics for twi continued Mnem...

Page 446: ...gisters Altered MSR EE Invalid Instruction Forms Reserved fields Programming Notes Execution of this instruction is privileged This instruction is typically used as part of a code sequence which can p...

Page 447: ...Registers Altered MSR EE Invalid Instruction Forms Reserved fields Programming Notes Execution of this instruction is privileged This instruction is typically used as part of a code sequence which ca...

Page 448: ...strset fm September 12 2002 xor XOR RA RS RB The contents of register RS are XORed with the contents of register RB the result is placed into register RA Registers Altered RA CR CR0 if Rc contains 1 x...

Page 449: ...02 Page 449 of 589 xori XOR Immediate RA RS 16 0 IM The IM field is extended to 32 bits by concatenating 16 0 bits on the left The contents of register RS are XORed with the extended IM field the resu...

Page 450: ...September 12 2002 xoris XOR Immediate Shifted RA RS IM 16 0 The IM field is extended to 32 bits by concatenating 16 0 bits on the right The contents of register RS are XORed with the extended IM field...

Page 451: ...to the processor func tions with which they are associated More information about the registers and register categories is provided in Section 2 2 Registers on page 47 and in the chapters describing t...

Page 452: ...239 DBDR Supervisor SPR 247 DBSR Supervisor SPR 244 DVC1 DVC2 Supervisor SPR 246 IAC1 IAC4 Supervisor SPR 245 Device Control Implemented outside core Supervisor DCR 53 Integer Processing GPR0 GPR31 U...

Page 453: ...er 12 2002 Page 453 of 589 Timer DEC Supervisor SPR 211 DECAR Supervisor write only SPR 211 TBL TBU User read Supervisor write SPR 209 TCR Supervisor SPR 215 TSR Supervisor SPR 216 Table 10 1 Register...

Page 454: ...ware will observe any newly set bit s If it were not for this behavior then software could erroneously clear bits which it had not yet observed as having been set and overlook the occurrence of certai...

Page 455: ...pervisor Read Write DAC2 Data Address Compare 2 0x13D Supervisor Read Write DVC1 Data Value Compare 1 0x13E Supervisor Read Write DVC2 Data Value Compare 2 0x13F Supervisor Read Write TSR Timer Status...

Page 456: ...x390 Supervisor Read Write DNV1 Data Cache Normal Victim 1 0x391 Supervisor Read Write DNV2 Data Cache Normal Victim 2 0x392 Supervisor Read Write DNV3 Data Cache Normal Victim 3 0x393 Supervisor Read...

Page 457: ...using a read modify write strategy read the register alter desired fields with logical instructions and then write the register 10 3 Device Control Registers Device Control Registers DCRs which are ar...

Page 458: ...User s Manual PPC440x5 CPU Core Preliminary Page 458 of 589 regsummIntro fm September 12 2002...

Page 459: ...detailed register information Register type if SPR the types of the other registers are the same as the register names CR GPR MSR Register number address Register programming model user or supervisor...

Page 460: ...11 DAPUIB Disable APU Instruction Broadcast 0 Enabled 1 Disabled instructions not broadcast to APU for decoding This mechanism is provided as a means of reduc ing power consumption when an auxilliary...

Page 461: ...data address is not on an operand boundary See Load and Store Alignment on page 117 24 27 Reserved 28 29 ICSLC Instruction Cache Speculative Line Count Number of additional lines 0 3 to fill on instru...

Page 462: ...the U fields in the data cache 14 DCMPEI Data Cache Modified bit Parity Error Insert 0 record even parity normal 1 record odd parity simulate parity error Controls inversion of parity bits recorded f...

Page 463: ...2 Page 463 of 589 24 TCS Timer Clock Select 0 CPU timer advances by one at each rising edge of the CPU input clock CPMC440CLOCK 1 CPU timer advances by one for each rising edge of the CPU timer clock...

Page 464: ...ondition Register CR 0 3 CR0 Condition Register Field 0 4 7 CR1 Condition Register Field 1 8 11 CR2 Condition Register Field 2 12 15 CR3 Condition Register Field 3 16 19 CR4 Condition Register Field 4...

Page 465: ...er s Manual regsumm440core fm September 12 2002 Page 465 of 589 CSRR0 SPR 0x03A Supervisor R W See Critical Save Restore Register 0 CSRR0 on page 168 Figure 10 4 Critical Save Restore Register 0 CSRR0...

Page 466: ...re fm September 12 2002 CSRR1 SPR 0x03B Supervisor R W See Critical Save Restore Register 1 CSRR1 on page 168 Figure 10 5 Critical Save Restore Register 1 CSRR1 0 31 Copy of the MSR when a critical in...

Page 467: ...egsumm440core fm September 12 2002 Page 467 of 589 CTR SPR 0x009 User R W See Count Register CTR on page 67 Figure 10 6 Count Register CTR 0 31 Count Used as count for branch conditional with decre me...

Page 468: ...nual Preliminary Page 468 of 589 regsumm440core fm September 12 2002 DAC1 DAC2 SPR 0x13C 0x13D Supervisor R W See Data Address Compare Registers DAC1 DAC2 on page 246 Figure 10 7 Data Address Compare...

Page 469: ...debug wait mode 5 BRT Branch Taken Debug Event 0 Disable branch taken debug event 1 Enable branch taken debug event Taken branches do not cause branch taken debug events if MSR DE 0 in internal debug...

Page 470: ...Debug Event 0 Disable DAC 2 read debug event 1 Enable DAC 2 read debug event 15 DAC2W DAC 2 Write Debug Event 0 Disable DAC 2 write debug event 1 Enable DAC 2 write debug event 16 RET Return Debug Ev...

Page 471: ...IAC 2 Effective Real 00 Effective MSR IS don t care 01 Reserved 10 Virtual MSR IS 0 11 Virtual MSR IS 1 8 9 IAC12M IAC 1 2 Mode 00 Exact match 01 Reserved 10 Range inclusive 11 Range exclusive Match...

Page 472: ...3 IAC4ER IAC 4 Effective Real 00 Effective MSR IS don t care 01 Reserved 10 Virtual MSR IS 0 11 Virtual MSR IS 1 24 25 IAC34M IAC 3 4 Mode 00 Exact match 01 Reserved 10 Range inclusive 11 Range exclus...

Page 473: ...n t care 01 Reserved 10 Virtual MSR DS 0 11 Virtual MSR DS 1 8 9 DAC12M DAC 1 2 Mode 00 Exact match 01 Address bit mask 10 Range inclusive 11 Range exclusive Match if address 0 31 DAC 1 2 0 31 two ind...

Page 474: ...umm440core fm September 12 2002 14 15 DVC2M DVC 2 Mode 00 Reserved 01 AND all bytes enabled by DVC2BE 10 OR all bytes enabled by DVC2BE 11 AND OR pairs of bytes enabled by DVC2BE 0 AND 1 OR 2 AND 3 16...

Page 475: ...Preliminary PPC440x5 CPU Core User s Manual regsumm440core fm September 12 2002 Page 475 of 589 DBDR SPR 0x3F3 Supervisor R W See Debug Data Register DBDR on page 247 Figure 10 11 Debug Data Register...

Page 476: ...reset 10 Chip reset 11 System reset This field is set upon any processor reset to a value indicating the type of reset 4 ICMP Instruction Completion Debug Event 0 Event didn t occur 1 Event occurred 5...

Page 477: ...ed 15 DAC2W DAC 2 Write Debug Event 0 Event didn t occur 1 Event occurred 16 RET Return Debug Event 0 Event didn t occur 1 Event occurred 17 29 Reserved 30 IAC12ATS IAC 1 2 Auto Toggle Status 0 Range...

Page 478: ...Register High DCDBTRH 0 23 TRA Tag Real Address Bits 0 23 of the lower 32 bits of the 36 bit real address associated with the cache line read by dcread 24 V Cache Line Valid 0 Cache line is not valid...

Page 479: ...odified dirty parity The parity for the modified dirty indicators for each of the four doublewords in the cache line read by dcread if CCR0 CRPE 1 otherwise 0 24 27 D Dirty Indicators The dirty modifi...

Page 480: ...Page 480 of 589 regsumm440core fm September 12 2002 DEAR SPR 0x03D Supervisor R W See Data Exception Address Register DEAR on page 170 Figure 10 15 Data Exception Address Register DEAR 0 31 Address o...

Page 481: ...r Preliminary PPC440x5 CPU Core User s Manual regsumm440core fm September 12 2002 Page 481 of 589 DEC SPR 0x016 Supervisor R W See Decrementer DEC on page 211 Figure 10 16 Decrementer DEC 0 31 Decreme...

Page 482: ...of 589 regsumm440core fm September 12 2002 DECAR SPR 0x036 Supervisor Write Only See Decrementer DEC on page 211 Figure 10 17 Decrementer Auto Reload DECAR 0 31 Decrementer auto reload value Copied t...

Page 483: ...0 DNV3 0 7 VNDXA Victim Index A for cache lines with EA 25 26 0b00 For all victim index fields the number of bits used to select the cache way for replacement depends on the implemented cache size See...

Page 484: ...DTV0 DTV3 0 7 VNDXA Victim Index A for cache lines with EA 25 26 0b00 For all victim index fields the number of bits used to select the cache way for replacement depends on the implemented cache size...

Page 485: ...x5 CPU Core User s Manual regsumm440core fm September 12 2002 Page 485 of 589 DVC1 DVC2 SPR 0x13E 0x13F Supervisor R W See Data Value Compare Registers DVC1 DVC2 on page 246 Figure 10 20 Data Value Co...

Page 486: ...e TFLOOR field varies depending on the implemented cache size See Table 4 3 on page 98 for more information 10 12 Reserved 13 20 TCEILING Transient Ceiling The number of bits in the TCEILING field var...

Page 487: ...Interrupt Trap Exception 0 Trap exception did not occur 1 Trap exception occurred 7 FP Floating Point Operation 0 Exception was not caused by a floating point instruction 1 Exception was caused by a...

Page 488: ...ruction 1 Instruction which caused the exception is a floating point CR updating instruction This is an implementation dependent field of the ESR and is not part of the PowerPC Book E Archi tecture Th...

Page 489: ...ry PPC440x5 CPU Core User s Manual regsumm440core fm September 12 2002 Page 489 of 589 GPR0 GPR31 User R W See General Purpose Registers GPRs on page 71 Figure 10 23 General Purpose Registers R0 R31 0...

Page 490: ...age 490 of 589 regsumm440core fm September 12 2002 IAC1 IAC4 SPR 0x138 0x13B Supervisor R W See Instruction Address Compare Registers IAC1 IAC4 on page 245 Figure 10 24 Instruction Address Compare Reg...

Page 491: ...5 CPU Core User s Manual regsumm440core fm September 12 2002 Page 491 of 589 ICDBDR SPR 0x3D3 Supervisor Read Only See icread Operation on page 112 Figure 10 25 Instruction Cache Debug Data Register I...

Page 492: ...32 bit effective address associated with the cache line read by icread 24 V Cache Line Valid 0 Cache line is not valid 1 Cache line is valid The valid indicator for the cache line read by icread 25 2...

Page 493: ...Debug Tag Register Low ICDBTRL 0 21 Reserved 22 TS Translation Space The address space portion of the virtual address associated with the cache line read by icread 23 TD Translation ID TID Disable 0...

Page 494: ...ers INV0 INV3 0 7 VNDXA Victim Index A for cache lines with EA 25 26 0b00 For all victim index fields the number of bits used to select the cache way for replacement depends on the implemented cache s...

Page 495: ...isters ITV0 ITV3 0 7 VNDXA Victim Index A for cache lines with EA 25 26 0b00 For all victim index fields the number of bits used to select the cache way for replacement depends on the implemented cach...

Page 496: ...s in the TFLOOR field varies depending on the implemented cache size See Table 4 3 on page 98 for more information 10 12 Reserved 13 20 TCEILING Transient Ceiling The number of bits in the TCEILING fi...

Page 497: ...5 Reserved 16 27 IVO Interrupt Vector Offset 28 31 Reserved Table 10 3 Interrupt Types Associated with each IVOR IVOR Interrupt Type IVOR0 Critical Input IVOR1 Machine Check IVOR2 Data Storage IVOR3 I...

Page 498: ...ual Preliminary Page 498 of 589 regsumm440core fm September 12 2002 IVPR SPR 0x03F Supervisor R W See Interrupt Vector Prefix Register IVPR on page 171 Figure 10 32 Interrupt Vector Prefix Register IV...

Page 499: ...440x5 CPU Core User s Manual regsumm440core fm September 12 2002 Page 499 of 589 LR SPR 0x008 User R W See Link Register LR on page 66 Figure 10 33 Link Register LR 0 31 Link Register contents Target...

Page 500: ...PLB interrupt request IRQ 1 Exception caused by Data Write PLB interrupt request IRQ 4 TLBP Translation Lookaside Buffer Parity Error 0 Exception not caused by TLB parity error 1 Exception caused by T...

Page 501: ...anual regsumm440core fm September 12 2002 Page 501 of 589 MCSRR0 SPR 0x23A Supervisor R W See Machine Check Save Restore Register 0 MCSRR0 on page 169 Figure 10 35 Machine Check Save Restore Register...

Page 502: ...September 12 2002 MCSRR1 SPR 0x23B Supervisor R W See Machine Check Save Restore Register 1 MCSRR1 on page 169 Figure 0 2 Machine Check Save Restore Register 1 MCSRR1 0 31 Copy of the MSR at the time...

Page 503: ...Enable U2 storage attribute control of store without allocate If MMUCR U2SWOAE 1 the U2 storage attribute overrides MMUCR SWOA 11 Reserved 12 DULXE Data Cache Unlock Exception Enable 0 Data cache unl...

Page 504: ...are disabled 1 External Input Decrementer and Fixed Interval Timer interrupts are enabled 17 PR Problem State 0 Supervisor state privileged instructions can be executed 1 Problem state privileged inst...

Page 505: ...if MSR FE0 1 precise mode 24 25 Reserved 26 IS Instruction Address Space 0 All instruction storage accesses are directed to address space 0 TS 0 in the relevant TLB entry 1 All instruction storage acc...

Page 506: ...CPU Core User s Manual Preliminary Page 506 of 589 regsumm440core fm September 12 2002 PID SPR 0x030 Supervisor R W See Process ID PID on page 151 Figure 10 38 Process ID PID 0 23 Reserved 24 31 PID P...

Page 507: ...Manual regsumm440core fm September 12 2002 Page 507 of 589 PIR SPR 0x11E Supervisor Read Only See Processor Identification Register PIR on page 76 Figure 10 39 Processor Identification Register PIR 0...

Page 508: ...0x11F Supervisor Read Only See Processor Version Register PVR on page 75 Figure 10 40 Processor Version Register PVR 0 11 OWN Owner Identifier Identifies the owner of a core 12 31 PVN Processor Versi...

Page 509: ...1 on page 135 18 U2 U2 Storage Attribute 0 U2 storage attribute is disabled 1 U2 storage attribute is enabled See Table 5 1 on page 135 19 U3 U3 Storage Attribute 0 U3 storage attribute is disabled 1...

Page 510: ...September 12 2002 SPRG0 SPRG7 SPR 0x104 0x107 User Supervisor Read Only SPR 0x110 0x113 Supervisor R W SPR 0x114 0x117 Supervisor Write Only See Special Purpose Registers General USPRG0 SPRG0 SPRG7 on...

Page 511: ...User s Manual regsumm440core fm September 12 2002 Page 511 of 589 SRR0 SPR 0x01A Supervisor R W See Save Restore Register 0 SRR0 on page 167 Figure 10 43 Save Restore Register 0 SRR0 0 29 Return addr...

Page 512: ...core fm September 12 2002 SRR1 SPR 0x01B Supervisor R W See Save Restore Register 1 SRR1 on page 167 Figure 10 44 Save Restore Register 1 SRR1 0 31 Copy of the MSR at the time of a non critical inter...

Page 513: ...er s Manual regsumm440core fm September 12 2002 Page 513 of 589 TBL SPR 0x10C User Supervisor Read Only SPR 0x11C Supervisor Write Only See Time Base on page 209 Figure 10 45 Time Base Lower TBL 0 31...

Page 514: ...Preliminary Page 514 of 589 regsumm440core fm September 12 2002 TBU SPR 0x10D User Supervisor Read Only SPR 0x11D Supervisor Write Only See Time Base on page 209 Figure 10 46 Time Base Upper TBU 0 31...

Page 515: ...r excep tion with TSR ENW WIS 0b11 This field can be set by software but cannot be cleared by software except by a software induced reset 4 WIE Watchdog Timer Interrupt Enable 0 Disable Watchdog Timer...

Page 516: ...Timer Interrupt Status 0 Watchdog Timer exception has not occurred 1 Watchdog Timer exception has occurred 2 3 WRS Watchdog Timer Reset Status 00 No Watchdog Timer reset has occurred 01 Core reset wa...

Page 517: ...e User s Manual regsumm440core fm September 12 2002 Page 517 of 589 USPRG0 SPR 0x100 User R W See Special Purpose Registers General USPRG0 SPRG0 SPRG7 on page 75 Figure 10 49 User Special Purpose Regi...

Page 518: ...y mtspr or by mcrxr 1 OV Overflow 0 No overflow has occurred 1 Overflow has occurred Can be set by mtspr or by integer or allocated instructions with the o option can be reset by mtspr by mcrxr or by...

Page 519: ...nded mnemonics are not included in the opcode list but allocated preserved and reserved nop opcodes are included A 1 Instruction Formats Instructions are four bytes long Instruction addresses are alwa...

Page 520: ...d is concatenated on the right with 0b00 and sign extended to 32 bits BF 6 8 Specifies a field in the CR used as a target in a compare or mcrf instruction BFA 11 13 Specifies a field in the CR used as...

Page 521: ...se register SPR This field represents the SPR Number SPRN with the upper and lower five bits reversed that is SPRF SPRN 5 9 SPRN 0 4 TO 6 10 Specifies the conditions on which to trap as described unde...

Page 522: ...rm A 1 2 4 D Form OPCD LI 0 6 31 Figure A 1 I Instruction Format OPCD BO BI BD AA LK 0 6 11 16 30 31 Figure A 2 B Instruction Format OPCD 1 0 6 11 16 30 31 Figure A 3 SC Instruction Format OPCD RT RA...

Page 523: ...WS XO OPCD RT RB XO OPCD RT XO OPCD RS RA RB XO Rc OPCD RS RA RB XO 1 OPCD RS RA RB XO OPCD RS RA NB XO OPCD RS RA WS XO OPCD RS RA SH XO Rc OPCD RS RA XO Rc OPCD RS RB XO OPCD RS XO OPCD BF L RA RB...

Page 524: ...D BC BI XO LK OPCD BF BFA XO OPCD XO 0 6 11 16 21 31 Figure A 6 XL Instruction Format OPCD RT SPRF XO OPCD RT DCRF XO OPCD RT FXM XO OPCD RS SPRF XO OPCD RS DCRF XO 0 6 11 16 21 31 Figure A 7 XFX Inst...

Page 525: ...always been assumed The assembler must enable the programmer to specify branch prediction To do this the assembler supports suffixes for the conditional branch mnemonics Predict branch to be taken Pr...

Page 526: ...tional relative LI target CIA 6 29 NIA CIA EXTS LI 20 268 ba Branch unconditional absolute LI target6 29 NIA EXTS LI 20 bl Branch unconditional relative LI target CIA 6 29 NIA CIA EXTS LI 20 LR CIA 4...

Page 527: ...Extended mnemonic for bcla 16 0 target LR CIA 4 bdnzlr Decrement CTR Branch if CTR 0 to address in LR Extended mnemonic for bclr 16 0 278 bdnzlrl Extended mnemonic for bclrl 16 0 LR CIA 4 bdnzf cr_bit...

Page 528: ...ded mnemonic for bca 18 0 target bdzl Extended mnemonic for bcl 18 0 target LR CIA 4 bdzla Extended mnemonic for bcla 18 0 target LR CIA 4 bdzlr Decrement CTR Branch if CTR 0 to address in LR Extended...

Page 529: ...ca 12 4 cr_field 2 target beql Extended mnemonic for bcl 12 4 cr_field 2 target LR CIA 4 beqla Extended mnemonic for bcla 12 4 cr_field 2 target LR CIA 4 beqctr cr_field Branch if equal to address in...

Page 530: ...CR CR0 if cr_field is omitted Extended mnemonic for bcctr 4 4 cr_field 0 275 bgectrl Extended mnemonic for bcctrl 4 4 cr_field 0 LR CIA 4 bgelr cr_field Branch if greater than or equal to address in L...

Page 531: ...cr_field is omitted Extended mnemonic for bcctr 4 4 cr_field 1 275 blectrl Extended mnemonic for bcctrl 4 4 cr_field 1 LR CIA 4 blelr cr_field Branch if less than or equal to address in LR Use CR CR0...

Page 532: ...field 2 target LR CIA 4 bnela Extended mnemonic for bcla 4 4 cr_field 2 target LR CIA 4 bnectr cr_field Branch if not equal to address in CTR Use CR CR0 if cr_field is omitted Extended mnemonic for bc...

Page 533: ..._field 0 target LR CIA 4 bnlla Extended mnemonic for bcla 4 4 cr_field 0 target LR CIA 4 bnlctr cr_field Branch if not less than to address in CTR Use CR CR0 if cr_field is omitted Extended mnemonic f...

Page 534: ...4 cr_field 3 target LR CIA 4 bnula Extended mnemonic for bcla 4 4 cr_field 3 target LR CIA 4 bnuctr cr_field Branch if not unordered to address in CTR Use CR CR0 if cr_field is omitted Extended mnemon...

Page 535: ...rget LR CIA 4 btctr cr_bit Branch if CRcr_bit 1 to address in CTR Extended mnemonic for bcctr 12 cr_bit 275 btctrl Extended mnemonic for bcctrl 12 cr_bit LR CIA 4 btlr cr_bit Branch if CRcr_bit 1 to a...

Page 536: ...ear right immediate n 32 RA 32 n 31 n0 Extended mnemonic for rlwinm RA RS 0 0 31 n 400 clrrwi Extended mnemonic for rlwinm RA RS 0 0 31 n CR CR0 cmp BF 0 RA RB Compare RA to RB signed Results in CR CR...

Page 537: ...by by 291 cror BT BA BB OR bit CRBA with CRBB Place result in CRBT 292 crorc BT BA BB OR bit CRBA with CRBB Place result in CRBT 293 crset bx Condition register set Extended mnemonic for creqv bx bx...

Page 538: ...B d RS RB i x y 0 do while x 8 y 0 x x 1 if di i 7 0 then y 1 else i i 8 RA x XER TBC x if Rc 1 then CR CR0 3 XER SO if y 1 then if x 5 then CR CR0 0 2 0b010 else CR CR0 0 2 0b100 else CR CR0 0 2 0b00...

Page 539: ...1 399 inslwi Extended mnemonic for rlwimi RA RS 32 b b b n 1 CR CR0 insrwi RA RS n b Insert from right immediate n 0 RA b b n 1 RS 32 n 31 Extended mnemonic for rlwimi RA RS 32 b n b b n 1 399 insrwi...

Page 540: ...address RA EA 331 lhzux RT RA RB Load halfword from EA RA 0 RB and pad left with zeroes RT 160 MS EA 2 Update the base address RA EA 332 lhzx RT RA RB Load halfword from EA RA 0 RB and pad left with z...

Page 541: ...RT MS EA 4 Update the base address RA EA 342 lwzux RT RA RB Load word from EA RA 0 RB and place in RT RT MS EA 4 Update the base address RA EA 343 lwzx RT RA RB Load word from EA RA 0 RB and place in...

Page 542: ...353 maclhw CR CR0 maclhwo XER SO OV maclhwo CR CR0 XER SO OV maclhwu RT RA RB prod0 31 RA 16 31 RB 0 15 temp0 32 prod0 31 RT RT temp1 32 356 maclhwu CR CR0 maclhwuo XER SO OV maclhwuo CR CR0 XER SO OV...

Page 543: ...r 12 2002 Page 543 of 589 mfcr RT Move from CR to RT RT CR 360 mfdcr RT DCRN Move from DCR to RT RT DCR DCRN 361 mfmsr RT Move from MSR to RT RT MSR 362 Table A 1 PPC440x5 Instruction Syntax Summary c...

Page 544: ...mfsprg0 mfsprg1 mfsprg2 mfsprg3 mfsprg4 mfsprg5 mfsprg6 mfsprg7 mfsrr0 mfsrr1 mfsrr2 mfsrr3 mfsu0r mftbl mftbu mftcr mftsr mfxer RT Move from special purpose register SPR SPRN Extended mnemonic for mf...

Page 545: ...in When msync completes all storage accesses initiated prior to msync will have completed 366 mtcr RS Move to Condition Register Extended mnemonic for mtcrf 0xFF RS 367 mtcrf FXM RS Move some or all o...

Page 546: ...r0 mtmcsrr1 mtpid mtpit mtpvr mtsgr mtsprg0 mtsprg1 mtsprg2 mtsprg3 mtsprg4 mtsprg5 mtsprg6 mtsprg7 mtsrr0 mtsrr1 mtsrr2 mtsrr3 mtsu0r mttbl mttbu mttcr mttsr mtxer mtzpr RS Move to SPR SPRN Extended...

Page 547: ...8 mulhwu CR CR0 mullhw RT RA RB RT 0 31 RA 16 31 RB16 31 signed 379 mullhw CR CR0 mullhwu RT RA RB RT 16 31 RA 0 15 RB 16 31 unsigned 380 mullhwu CR CR0 mulli RT RA IM Multiply RA and IM signed Place...

Page 548: ...wo XER SO OV nmaclhwo CR CR0 XER SO OV nmaclhws RT RA RB prod0 31 RA 16 31 RB 16 31 temp0 32 prod0 31 RT if prod0 RT0 RT0 temp1 then RT RT0 31 RT0 else RT temp1 32 390 nmaclhws CR CR0 nmaclhwso XER SO...

Page 549: ...Rotate left RA ROTL RS RB 27 31 Extended mnemonic for rlwnm RA RS RB 0 31 403 rotlw Extended mnemonic for rlwnm RA RS RB 0 31 CR CR0 rotlwi RA RS n Rotate left immediate RA ROTL RS n Extended mnemonic...

Page 550: ...26 0 then m MASK n 31 else m 320 RA r m 408 srw CR CR0 srwi RA RS n Shift right immediate n 32 RA n 31 RS 0 31 n RA 0 n 1 n0 Extended mnemonic for rlwinm RA RS 32 n n 31 400 srwi Extended mnemonic fo...

Page 551: ...A RB Store consecutive bytes in memory starting at EA RA 0 RB Number of bytes n XER TBC Bytes are unstacked from CEIL n 4 consecutive registers starting with RS GPR 0 is consecutive to GPR 31 421 stw...

Page 552: ...ic for subfco RT RB RA CR CR0 XER SO OV subf RT RA RB Subtract RA from RB RT RA RB 1 429 subf CR CR0 subfo XER SO OV subfo CR CR0 XER SO OV subfc RT RA RB Subtract RA from RB RT RA RB 1 Place carry ou...

Page 553: ...tract IM 160 from RA 0 Place result in RT Extended mnemonic for addis RT RA IM 261 tlbre RT RA WS tlbentry TLB RA 26 31 if WS 0 RT 0 27 tlbentry EPN V TS SIZE RT 28 31 40 MMUCR STID tlbentry TID else...

Page 554: ...processors For the PPC440x5 core tlbsync is a no op 438 tlbwe RS RA WS tlbentry TLB RA 26 31 if WS 0 tlbentry EPN V TS SIZE RS 0 27 tlbentry TID MMUCR STID else if WS 1 tlbentry RPN RS 0 21 tlbentry E...

Page 555: ...twlle Trap if RA logically less than or equal to RB Extended mnemonic for tw 6 RA RB twllt Trap if RA logically less than RB Extended mnemonic for tw 2 RA RB twlng Trap if RA logically not greater th...

Page 556: ...ogically less than EXTS IM Extended mnemonic for twi 2 RA IM twlngi Trap if RA logically not greater than EXTS IM Extended mnemonic for twi 6 RA IM twlnli Trap if RA logically not less than EXTS IM Ex...

Page 557: ...e PPC440x5 core A 4 Preserved Instruction Opcodes The preserved instruction class is provided to support backward compatibility with the PowerPC Architecture and or earlier versions of the PowerPC Boo...

Page 558: ...lable for future versions of PowerPC Book E architecture That is future versions of PowerPC Book E may define any of these instructions to perform new functions or make them available for implementati...

Page 559: ...ented and thus included in Table A 5 These instructions will be handled as reserved illegal by the PPC440x5 Reserved instructions These include all of the reserved opcodes as defined by Appendix A 5 o...

Page 560: ...RA RB 350 machhws machhwso machhwso 4 110 622 XO nmachhws RT RA RB 388 nmachhws nmachhwso nmachhwso 4 136 X mulchwu RT RA RB 374 mulchwu 4 140 652 XO macchwu RT RA RB 348 macchwu macchwuo machhwuo 4...

Page 561: ...maclhw maclhwo maclhwo 4 430 942 XO nmaclhw RT RA RB 389 nmaclhw nmaclhwo nmaclhwo 4 460 972 XO maclhwsu RT RA RB 355 maclhwsu maclhwsuo maclhwsuo 4 492 1004 XO maclhws RT RA RB 354 maclhws maclhwso...

Page 562: ...225 XL crnand BT BA BB 290 19 257 XL crand BT BA BB 287 19 289 XL creqv BT BA BB 289 19 417 XL crorc BT BA BB 293 19 449 XL cror BT BA BB 292 19 528 XL bcctr BO BI 275 bcctrl 20 M rlwimi RA RS SH MB M...

Page 563: ...31 23 X lwzx RT RA RB 344 31 24 X slw RA RS RB 405 slw 31 26 X cntlzw RA RS 286 cntlzw 31 28 X and RA RS RB 264 and 31 32 X cmpl BF 0 RA RB 284 31 40 552 XO subf RT RA RB 429 subf subfo subfo 31 54 X...

Page 564: ...eo 31 144 XFX mtcrf FXM RS 367 31 146 X mtmsr RS 369 31 150 X stwcx RS RA RB 424 31 151 X stwx RS RA RB 428 31 163 X wrteei E 447 31 183 X stwux RS RA RB 427 31 200 712 XO subfze RT RA RB 434 subfze s...

Page 565: ...448 xor 31 323 XFX mfdcr RT DCRN 361 31 339 XFX mfspr RT SPRN 363 31 343 X lhax RT RA RB 328 31 371 XFX mftb RT SPRN 557 31 375 X lhaux RT RA RB 327 31 407 X sthx RS RA RB 417 31 412 X orc RA RS RB 3...

Page 566: ...1 661 X stswx RS RA RB 421 31 662 X stwbrx RS RA RB 423 31 690 Reserved nop 558 31 722 Reserved nop 558 31 725 X stswi RS RA NB 418 31 754 Reserved nop 558 31 758 X dcba RA RB 295 31 790 X lhbrx RT RA...

Page 567: ...RA 321 35 D lbzu RT D RA 322 36 D stw RS D RA 422 37 D stwu RS D RA 426 38 D stb RS D RA 409 39 D stbu RS D RA 410 40 D lhz RT D RA 330 41 D lhzu RT D RA 331 42 D lha RT D RA 325 43 D lhau RT D RA 326...

Page 568: ...User s Manual PPC440x5 CPU Core Preliminary Page 568 of 589 instalfa fm September 12 2002...

Page 569: ...ores can only use the L Pipe Branches CR updates XER updates o forms of arithmetic instructions multiply divide system instructions such as rfi and sc and any SPR accesses mtspr mfspr can only use the...

Page 570: ...ion for a string compare oper ation to determine which string is greater than another If the string multiple is for a relatively small num ber of registers or the expansion into discrete loads stores...

Page 571: ...524 and 264 and 264 andc 265 andc 265 andi 266 andis 267 arithmetic compare 71 arrays shadow TLB 151 asynchronous interrupt class 159 attributes storage 145 Auxiliary Processor Unavailable interrupt...

Page 572: ...73 bnectr 276 bnectrl 276 bnel 273 bnela 273 bnelr 280 bnelrl 280 bng 273 bnga 273 bngctr 277 bngctrl 277 bngl 273 bngla 273 bnglr 281 bnglrl 281 bnl 273 bnla 273 bnlctr 277 bnlctrl 277 bnll 273 bnlla...

Page 573: ...li 285 cmplw 284 cmplwi 285 cmpw 282 cmpwi 283 cntlzw 286 cntlzw 286 code self modifying 106 coherence data cache 124 coherency instruction cache 106 compare arithmetic 71 logical 71 Condition Registe...

Page 574: ...escription 300 functional description 126 operation summary 125 dcbz 302 operation summary 125 DCC data cache controller control 125 debug 125 features 115 operations 116 dccci 304 operation summary 1...

Page 575: ...es for all other instructions 208 allocated load and store instructions 203 branch instructions 207 floating point load and store instructions 203 integer load store and cache management instruc tions...

Page 576: ...6 bnel 273 bnela 273 bnelr 280 bnelrl 280 bng 273 bnga 273 bngctr 277 bngctrl 277 bngl 273 bngla 273 bnglr 281 bnglrl 281 bnl 273 bnla 273 bnlctr 277 bnlctrl 277 bnll 273 bnlla 273 bnllr 281 bnllrl 28...

Page 577: ...ubfco 430 for tw 441 for twi 444 inslwi 399 inslwi 399 insrwi 399 insrwi 399 li 258 lis 261 mr 392 mr 392 mtcr 367 nop 394 not 391 not 391 rotlw 403 rotlw 403 rotlwi 401 rotlwi 401 rotrwi 401 rotrwi 4...

Page 578: ...eration summary 108 icbt formal description 314 functional description 111 operation summary 108 ICC instruction cache controller control 108 debug 108 features 103 operations 104 iccci 316 operation...

Page 579: ...331 lhzux 332 lhzx 333 lmw 334 lswi 335 lswx 337 lwarx 339 lwz 341 lwzu 342 lwzux 343 lwzx 344 macchw 345 macchws 346 macchwsu 347 macchwu 348 machhw 349 machhwsu 351 machhwu 352 maclhw 353 maclhws 3...

Page 580: ...nstruction cache array organization and operation 95 instruction cache coherency 106 instruction cache controller See ICC instruction cache synonyms 107 instruction classes 53 instruction complete ICM...

Page 581: ...store and cache management exception priorities for 202 mfmsr 165 mtmsr 165 opcodes 559 partially executed 164 preserved instruction opcodes 557 preserved exception priorities for 207 privileged 80 p...

Page 582: ...ssor unavailable 191 data storage 181 data TLB error 193 debug 195 decrementer 191 definitions 175 external inputs 185 fixed interval timer 192 floating point unavailable 190 instruction storage 184 i...

Page 583: ...mulhhwu 376 mulhwu 378 mulhwu 378 mullhw 379 mullhwu 380 mulli 381 mullw 382 mullw 382 mullwo 382 mullwo 382 N nand 383 nand 383 neg 384 neg 384 nego 384 nego 384 nmacchw 385 nmacchws 386 nmachhw 387...

Page 584: ...DECAR 211 482 DNV0 DNV3 483 DTV0 DTV3 484 DVC1 DVC2 246 DVLIM 486 ESR 172 487 GPR0 GPR31 489 GPRs 71 IAC1 IAC4 485 490 IAC1 IAC4 245 ICDBDR 491 ICDBTRH 492 ICDBTRL 493 interrupt processing 165 INV0 IN...

Page 585: ...stb 409 stbu 410 stbux 411 stbx 412 sth 413 sthbrx 414 sthu 415 sthux 416 sthx 417 stmw 418 storage access ordering 124 storage attributes caching inhibited 145 endian 146 guarded 146 Memory Coherence...

Page 586: ...ities 217 TCR 215 TSR 216 watchdog timer 213 watchdog timer state machine 215 TLB entry fields E 137 EPN 135 ERPN 136 G 137 I 136 M 137 RPN 136 SIZE 135 TID 135 TS 135 U0 136 U1 136 U2 136 U3 136 UR 1...

Page 587: ...vents 237 units memeory management 32 user mode 80 USPRG0 75 517 W storage attribute 145 Watchdog Timer interrupt 192 watchdog timer interrupts 192 write through required 145 writing the time base 210...

Page 588: ...User s Manual PPC440x5 CPU Core Preliminary Page 588 of 583 ppc440x5IX fm September 12 2002...

Page 589: ...t revisions summarized by chapter Ch 2 CCR1 updated Ch 4 CCR0 and CCR1 updated Sections on data cache parity insertion and simulating parity errors revised Ch 6 Revised MCSR MCSRR0 MCSRR1 and descript...

Page 590: ......

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