IBM PPC440X5 CPU Core, User Manual

Page: 83 / 590

User’s Manual
Preliminary PPC440x5 CPU Core
prgmodel.fm.
September 12, 2002
Page 83 of 589
XYZ fetch and execute the instruction at address XYZ
In this sequence, the isync instruction does not guarantee that the XYZ instruction is fetched after the
store has occurred to memory. There is no guarantee which XYZ instruction will execute; either the old
version or the new (stored) version might.
2. Now consider the required self-modifying code sequence:
stw Write new instruction to data cache
dcbst Push the new instruction from the data cache to memory
msync Guarantee that dcbst completes before subsequent instructions begin
icbi invalidate old copy of instruction in instruction cache
msync Guarantee that icbi completes before subsequent instructions begin
isync force context synchronization, discard ed instructions and re-fetch, fetch of
stored instruction guaranteed to get new value
3. This final example illustrates the use of
isync with context changes to the debug facilities
mtdbcr0 Enable the instruction address compare (IAC) debug event
isync Wait for the new Debug Control Register 0 (DBCR0) context to be established
XYZ This instruction is at the IAC address; an isync is necessary to guarantee that the
IAC event is recognized on the execution of this instruction; without the isync, the
XYZ instruction may be prefetched and dispatched to execution before
recognizing that the IAC event has been enabled.
2.10.2 Execution Synchronization
Execution synchronization is a subset of context synchronization. An execution synchronizing operation
satisfies the first two requirements of context synchronizing operations, but not the latter two. That is, execu-
tion synchronizing operations guarantee that preceding instructions execute in the “old” context, but do not
guarantee that subsequent instructions operate in the “new” context. An example of a scenario requiring
execution synchronization would be just before the execution of a TLB-updating instructions (such as tlbwe).
An execution synchronizing instruction should be executed to guarantee that all preceding storage access
instructions have performed their address translations before executing tlbwe to invalidate an entry which
might be used by those preceding instructions.
There are four execution synchronizing instructions:
mtmsr, wrtee, wrteei, and msync. Of course, all
context synchronizing instruction are also implicitly execution synchronizing, since context synchronization is
a superset of execution synchronization.
Note that PowerPC Book-E imposes additional requirements on updates to MSR[EE] (the external interrupt
enable bit). Specifically, if a
mtmsr, wrtee, or wrteei instruction sets MSR[EE] = 1, and an External Input,
Decrementer, or Fixed Interval Timer exception is pending, the interrupt must be taken before the instruction
that follows the MSR[EE]-updating is executed. In this sense, these MSR[EE]-updating instructions can be
PVR
OWN System-dependent PVR[OWN] value (after reset and otherwise) is specified by core input signals
PVN System-dependent PVR[PVN] value (after reset and otherwise) is specified by core input signals