IBM PPC440X5 CPU Core, User Manual

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User’s Manual
PPC440x5 CPU Core Preliminary
Page 232 of 589
debug.fm.
September 12, 2002
Event on page 226 describes the DAC conditions. In addition to the DAC conditions, there are two DVC regis-
ters on the PPC440x5, DVC1 and DVC2. The DVC registers can be used to specify two independent, 4-byte
data values, which are selectively compared against the data being accessed by a given load, store, or cache
management instruction.
When a DVC event occurs, the corresponding DBSR[DAC1R, DAC1W, DAC2R, DAC2W] bit is set. These
same DBSR bits are shared by DAC debug events.
8.3.3.1 DVC Debug Event Fields
In addition to the DAC debug event fields described in DAC Debug Event Fields on page 226, and the DVC
registers themselves, there are two fields in DBCR2 which are used to specify the DVC conditions, as follows:
DVC Byte Enable Field
DBCR2[DVC1BE, DVC2BE] are the individual DVC byte enable fields for the two DVC events.
When one or the other (or both) of these fields is disabled (by being set to 4b0000), the
corresponding DVC debug event is disabled (the corresponding DAC debug event may still be
enabled, as determined by the DAC debug event enable field of DBCR0). When either one or
both of these fields is enabled (by being set to a non-zero value), then the corresponding DVC
debug event is enabled.
Each bit of a given DVC byte enable field corresponds to a byte position within an aligned word of
memory. For a given aligned word of memory, the byte offsets (or “byte lanes”) within that word
are numbered 0, 1, 2, and 3, starting from the left-most (most significant) byte of the word.
Accordingly, bits 0:3 of a given DVC byte enable field correspond to bytes 0:3 of an aligned word
of memory being accessed.
For an access to “match” the DVC conditions for a given byte, the access must be actually
transferring data on that given byte position and the data must match the corresponding byte
value within the DVC register.
For each storage access, the DVC comparison is made against the bytes that are being
accessed within the aligned word of memory containing the starting byte of the transfer. For
example, consider a load word instruction with a starting data address of x01. The four bytes from
memory are located at addresses 0x01–0x04, but the aligned word of memory containing the
starting byte consists of addresses 0x00–0x03. Thus the only bytes being accessed within the
aligned word of memory containing the starting byte are the bytes at addresses 0x01–0x03, and
only these bytes are considered in the DVC comparison. The byte transferred from address 0x04
is not considered.
DVC Mode Field
DBCR2[DVC1M, DVC2M] are the individual DVC mode fields for the two DVC events. Each one
of these fields specifies the particular data value comparison mode for the corresponding DVC
debug event. There are three comparison modes supported by the PPC440x5:
• AND comparison mode (DBCR2[DVC1M, DVC2M] = 0b01)
In this mode, all data byte lanes enabled by a DVC byte enable field must be being accessed and
must match the corresponding byte data value in the corresponding DVC1 or DVC2 register.
• OR comparison mode (DBCR2[DVC1M, DVC2M] = 0b10)