IBM PPC440X5 CPU Core, User Manual

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User’s Manual
PPC440x5 CPU Core Preliminary
Page 186 of 589
intrupts.fm.
September 12, 2002
• An integer load or store instruction that references a data storage operand that is not aligned on an oper-
and-sized boundary, when CCR0[FLSTA] is 1. Load and store multiple instructions are considered to ref-
erence word operands, and hence word-alignment is required for the target address of these instructions
when CCR0[FLSTA] is 1. Load and store string instructions are considered to reference byte operands,
and hence they cannot cause an Alignment exception due to CCR0[FLSTA] being 1, regardless of the tar-
get address alignment.
• A floating-point or auxiliary processor load or store instruction that references a data storage operand
that crosses a quadword (16 byte) boundary.
• A floating-point or auxiliary processor load or store instruction that references a data storage operand
that is not aligned on an operand-sized boundary, when the attached processing unit indicates to the
PPC440x5 core that the instruction requires operand-alignment.
• A floating-point or auxiliary processor load or store instruction that references a data storage operand
that is not aligned on a word boundary, when the attached processing unit indicates to the PPC440x5
core that the instruction requires word-alignment.
• A dcbz instruction that targets a memory page that is either write-through required or caching inhibited.
If a stwcx. instruction causes an Alignment exception, and the processor does not have the reservation from
a lwarx instruction, then an Alignment interrupt still occurs.
Programming Note: The architecture does not support the use of an unaligned effective
address by the lwarx and stwcx. instructions. If an Alignment
interrupt occurs due to the attempted execution of one of these
instructions, the Alignment interrupt handler must not attempt to
emulate the instruction, but instead should treat the instruction as a
programming error.
When an Alignment interrupt occurs, the processor suppresses the execution of the instruction causing the
Alignment exception, the interrupt processing registers are updated as indicated below (all registers not listed
are unchanged), and instruction execution resumes at address IVPR[IVP] || IVOR5[IVO] || 0b0000.
Save/Restore Register 0 (SRR0)
Set to the effective address of the instruction causing the Alignment interrupt.
Save/Restore Register 1 (SRR1)
Set to the contents of the MSR at the time of the interrupt.
Machine State Register (MSR)
CE, ME, DE Unchanged.
All other MSR bits set to 0.
Data Exception Address Register (DEAR)
Set to the effective address of the target data operand as calculated by the instruction caus-
ing the Alignment exception. Note that for dcbz, this effective address is not necessarily the
address of the first byte of the targeted cache block, but could be the address of any byte
within the block (it will be the address calculated by the dcbz instruction).