IBM PPC440X5 CPU Core, User Manual

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User’s Manual
PPC440x5 CPU Core Preliminary
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debug.fm.
September 12, 2002
counter will contain the address of that instruction, and that instruction’s execution will have been
suppressed. Conversely, if the DAC debug event is processed after the completion of the
instruction causing the event, then the program counter will contain the address of some
instruction after the one which caused the event. Whether or not the DAC debug event
processing occurs before or after the completion of the instruction depends on the particular
circumstances surrounding the instruction’s execution, the details of which are generally beyond
the scope of this document.
Similarly, when operating in internal debug mode with Debug interrupts enabled (MSR[DE] = 1),
the occurrence of a DAC debug event is recorded in the DBSR and will generate a Debug
interrupt with CSRR0 set to the address of the instruction which caused the DAC debug event, or
to the address of some subsequent instruction, depending upon whether the event is processed
before or after the instruction completes.
When operating in internal debug mode (and not also in external debug mode nor debug wait
mode) with Debug interrupts disabled (MSR[DE] = 0), then a DAC debug event will set the
corresponding DAC field of the DBSR, along with the Imprecise Debug Event (IDE) field of the
DBSR. Instruction execution continues, and a Debug interrupt will occur if and when MSR[DE] is
set to 1, thereby enabling Debug interrupts, assuming software has not cleared the DAC debug
event status from the DBSR in the meantime. Upon such a “delayed” interrupt, the Debug
interrupt handler software may query the DBSR[IDE] field to determine that the Debug interrupt
has occurred imprecisely.
When operating in trace mode, the occurrence of a DAC debug event simply sets the
corresponding DAC field of the DBSR and is indicated over the trace interface, and instruction
execution continues. DBCR2[DAC12A] does not affect the processing of DAC debug events
when operating in trace mode.
8.3.2.3 DAC Debug Events Applied to Instructions that Result in Multiple Storage Accesses
Certain misaligned load and store instructions are handled by making multiple, independent storage
accesses. Similarly, load and store multiple and string instructions which access more than one register result
in more than one storage access. Load and Store Alignment on page 117 provides a detailed description of
the circumstances that lead to such multiple storage accesses being made as the result of the execution of a
single instruction.
Whenever the execution of a given instruction results in multiple storage accesses, the data address of each
access is independently considered for whether or not it will cause a DAC debug event.
8.3.2.4 DAC Debug Events Applied to Various Instruction Types
Various special cases apply to the cache management instructions, the store word conditional indexed
(stwcx.) instruction, and the load and store string indexed (lswx, stswx) instructions, with regards to DAC
debug events. These special cases are as follows:
dcbz, dcbi
The
dcbz and dcbi instructions are considered “stores” with respect to both storage access
control and DAC debug events. The dcbz instruction directly changes the contents of a given
storage location, whereas the dcbi instruction can indirectly change the contents of a given
storage location by invalidating data which has been modified within the data cache, thereby
“restoring” the value of the location to the “old” contents of memory. As “store” operations, they
may cause DAC write debug events.