IBM PPC440X5 CPU Core, User Manual

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divwu
Divide Word Unsigned
PPC440x5 CPU Core User’s Manual
Preliminary
Page 308 of 589
instrset.fm.
September 12, 2002
divwu
Divide Word Unsigned
(RT)
←
(RA)
÷
(RB)
The contents of register RA are divided by the contents of register RB. The quotient is placed into register RT.
The dividend and the divisor are interpreted as unsigned integers. The quotient is the unique unsigned
integer that satisfies:
dividend = (quotient
×
divisor) + remainder
If an attempt is made to perform (
n
÷
0), the contents of register RT are undefined; if the Rc also contains 1,
the contents of CR[CR0]
0:2
are also undefined. The invalid division operation also sets XER[OV, SO] (and
CR[CR0]
3
if Rc contains 1) to 1 if the OE field contains 1.
Registers Altered
• RT
• CR[CR0] if Rc contains 1
• XER[OV, SO] if OE contains 1
Programming Note
The 32-bit remainder can be calculated using the following sequence of instructions
divwu RT,RA,RB # RT = quotient
mullw RT,RT,RB # RT = quotient
×
divisor
subf RT,RT,RA # RT = remainder
This sequence does not calculate the correct result if the divisor is 0.
divwu RT, RA, RB OE=0, Rc=0
divwu. RT, RA, RB OE=0, Rc=1
divwuo RT, RA, RB OE=1, Rc=0
divwuo. RT, RA, RB OE=1, Rc=1
31 RT RA RB OE 459 Rc
0 6 11 16 21 22 31