IBM PPC440X5 CPU Core, User Manual

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dcbtst
Data Cache Block Touch for Store
PPC440x5 CPU Core User’s Manual
Preliminary
Page 300 of 589
instrset.fm.
September 12, 2002
dcbtst
Data Cache Block Touch for Store
EA
←
(RA|0) + (RB)
DCBTST(EA)
An effective address (EA) is formed by adding an index to a base address. The index is the contents of
register RB. The base address is 0 if the RA field is 0 and is the contents of register RA otherwise.
If the data block at the EA is not in the data cache and the memory page referenced by the EA address is
marked as cacheable, the data block is loaded into the data cache.
If the data block at the EA is in the data cache, or if the memory page referenced by the EA is marked as
caching inhibited, no operation is performed.
This instruction is not allowed to cause Data Storage interrupts nor Data TLB Error interrupts. If execution of
the instruction causes either of these types of exception, then no operation is performed, and no interrupt
occurs.
If instruction bit 31 contains 1, the contents of CR[CR0] are undefined.
Registers Altered
• None
Invalid Instruction Forms
• Reserved fields
Programming Notes
The
dcbtst instruction allows a program to begin a cache block fetch from main storage before the program
needs the data. The program can later store data from GPRs into the cache block, without incurring the
latency of a cache miss.
Architecturally, dcbtst is intended to bring a cache block into the data cache in a manner which will permit
future instructions to store to that block efficiently. For example, in an implementation which supports the
“MESI” cache coherency protocol, the block would be brought into the cache in “Exclusive” mode, allowing
the block to be stored to without having to broadcast any coherency operations on the system bus. However,
since the PPC440x5 core does not support hardware-enforcement of multiprocessor coherency, there is no
distinction between a block being brought in for a read or a write, and hence the implementation of the
dcbtst
instruction is identical to the implementation of the dcbt instruction.
Exceptions
This instruction is considered a “load” with respect to Data Storage exceptions. See Data Storage Interrupt on
page 181 for more information.
dcbtst RA, RB
31 RA RB 246
0 6 11 16 21 31