IBM PPC440X5 CPU Core, User Manual

Page: 439 / 590

tlbwe
TLB Write Entry
Preliminary PPC440x5 CPU Core User’s Manual
instrset.fm.
September 12, 2002
Page 439 of 589
tlbwe
TLB Write Entry
tlbentry
←
TLB[(RA)
26:31
]
if WS = 0
tlbentry[EPN,V,TS,SIZE]
←
(RS)
0:27
tlbentry[TID]
←
MMUCR[STID]
else if WS = 1
tlbentry[RPN]
←
(RS)
0:21
tlbentry[ERPN]
←
(RS)
28:31
else if WS = 2
tlbentry[U0,U1,U2,U3,W,I,M,G,E]
←
(RS)
16:24
tlbentry[UX,UW,UR,SX,SW,SR]
←
(RS)
26:31
else tlbentry
←
undefined
The contents of the specified portion of the selected TLB entry are replaced with the contents of register RS
(and also MMUCR[STID] if WS = 0).
Parity check bits are automatically calculated and stored in the TLB entry as the tlbwe is executed. The
contents of the RS register in the TPAR, PAR1, and PAR2 fields (for WS=0,1,or 2, respectively) is ignored by
tlbwe; the parity is calculated from the other data bits being written to the TLB entry.
The contents of RA are used as an index into the TLB. If this value is greater than the index of the highest
numbered TLB entry (63), the results are undefined.
The WS field specifies which portion of the TLB entry is replaced by the contents of RS. If WS = 0, the TID
field of the selected TLB entry is replaced by the value in MMUCR[STID]. See Memory Management on
page 133 for descriptions of the TLB entry fields.
If the value of the WS field is greater than 2, the instruction form is invalid and the result is undefined.
If instruction bit 31 contains 1, the contents of CR[CR0] are undefined.
Registers Altered
• None
Invalid Instruction Forms
• Reserved fields
• Invalid WS value
Programming Note
Execution of this instruction is privileged.
tlbwe RS, RA, WS
31 RS RA WS 978
0 6 11 16 21 31