User’s Manual
PPC440x5 CPU Core
Preliminary
Page 58 of 589
prgmodel.fm.
September 12, 2002
an “indexed” form (in which the address is formed by adding the contents of the RA and RB GPRs) and a
“base + displacement” form (in which the address is formed by adding a 16-bit signed immediate value (spec-
ified as part of the instruction) to the contents of GPR RA. See the detailed instruction descriptions in Instruc-
tion Set on page 249.
2.4.1.2 Integer Arithmetic Instructions
Arithmetic operations are performed on integer or ordinal operands stored in registers. Instructions that
perform operations on two operands are defined in a three-operand format; an operation is performed on the
operands, which are stored in two registers. The result is placed in a third register. Instructions that perform
operations on one operand are defined in a two-operand format; the operation is performed on the operand in
a register and the result is placed in another register. Several instructions also have immediate formats in
which one of the source operands is a field in the instruction.
Most integer arithmetic instructions have versions that can update CR[CR0] and/or XER[SO, OV] (Summary
Overflow, Overflow), based on the result of the instruction. Some integer arithmetic instructions also update
XER[CA] (Carry) implicitly. See Integer Processing on page 71 for more information on how these instruc-
tions update the CR and/or the XER.
Table 2-6 lists the integer arithmetic instructions in the PPC440x5. In the table, the syntax “[
o]” indicates that
the instruction has both an “o” form (which updates the XER[SO,OV] fields) and a “non-o” form. Similarly, the
syntax “[
.]” indicates that the instruction has both a “record” form (which updates CR[CR0]) and a “non-
record” form.
Table 2-5. Integer Storage Access Instructions
Loads
Stores
Byte
Halfword
Word
Multiple/String
Byte
Halfword
Word
Multiple/String
lbz
[
u
][
x
]
lha
[
u
][
x
]
lhbrx
lhz
[
u
][
x
]
lwarx
lwbrx
lwz
[
u
][
x
]
lmw
lswi
lswx
stb
[
u
][
x
]
sth
[
u
][
x
]
sthbrx
stw
[
u
][
x
]
stwbrx
stwcx.
stmw
stswi
stswx
Table 2-6. Integer Arithmetic Instructions
Add
Subtract
Multiply
Divide
Negate
add
[
o
][
.
]
addc
[
o
][
.
]
adde
[
o
][
.
]
addi
addic
[.]
addis
addme
[
o
][
.
]
addze
[
o
][
.
]
subf
[
o
][
.
]
subfc
[
o
][
.
]
subfe
[
o
][
.
]
subfic
subfme
[
o
][
.
]
subfze
[
o
][
.
]
mulhw
[
.
]
mulhwu
[
.
]
mulli
mullw
[
o
][
.
]
divw
[
o
][
.
]
divwu
[
o
][
.
]
neg
[
o
][
.
]
Summary of Contents for PPC440X5 CPU Core
Page 1: ...PPC440x5 CPU Core User s Manual Preliminary SA14 2613 02 September 12 2002 Title Page...
Page 22: ...User s Manual PPC440x5 CPU Core Preliminary Page 22 of 583 ppc440x5LOT fm September 12 2002...
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Page 38: ...User s Manual PPC440x5 CPU Core Preliminary Page 38 of 589 overview fm September 12 2002...
Page 94: ...User s Manual PPC440x5 CPU Core Preliminary Page 94 of 589 init fm September 12 2002...
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Page 158: ...User s Manual PPC440x5 CPU Core Preliminary Page 158 of 589 mmu fm September 12 2002...
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