IBM PPC440X5 CPU Core, User Manual

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User’s Manual
PPC440x5 CPU Core Preliminary
Page 178 of 589
intrupts.fm.
September 12, 2002
6.5.1 Critical Input Interrupt
A Critical Input interrupt occurs when no higher priority exception exists, a Critical Input exception is
presented to the interrupt mechanism, and MSR[CE] = 1. A Critical Input exception is caused by the activa-
tion of an asynchronous input to the PPC440x5 core. Although the only mask for this interrupt type within the
core is the MSR[CE] bit, system implementations typically provide an alternative means for independently
masking the interrupt requests from the various devices which collectively may activate the PPC440x5 core
Critical Input interrupt request input.
Note: MSR[CE] also enables the Watchdog Timer interrupt.
When a Critical Input interrupt occurs, the interrupt processing registers are updated as indicated below (all
registers not listed are unchanged), and instruction execution resumes at address IVPR[IVP] || IVOR0[IVO] ||
0b0000.
Critical Save/Restore Register 0 (CSRR0)
Set to the effective address of the next instruction to be executed.
Critical Save/Restore Register 1 (CSRR1)
Set to the contents of the MSR at the time of the interrupt.
Machine State Register (MSR)
ME Unchanged.
All other MSR bits set to 0.
Programming Note: Software is responsible for taking any action(s) that are required by
the implementation in order to clear any Critical Input exception status
(such that the Critical Input interrupt request input signal is
deasserted) before reenabling MSR[CE], in order to avoid another,
redundant Critical Input interrupt
.
6.5.2 Machine Check Interrupt
A Machine Check interrupt occurs when no higher priority exception exists, a Machine Check exception is
presented to the interrupt mechanism, and MSR[ME] = 1. The PowerPC architecture specifies Machine
Check interrupts as neither synchronous nor asynchronous, and indeed the exact causes and details of
handling such interrupts are implementation dependent. Regardless, for this particular processor core, it is
useful to describe the handling of interrupts caused by various types of Machine Check exceptions in those
terms. The PPC440x5 core includes four types of Machine Check exceptions. They are:
Instruction Synchronous Machine Check exception
A Instruction Synchronous Machine Check exception is caused when timeout or read error is
signaled on the instruction read PLB interface during an instruction fetch operation.
Such an exception is not presented to the interrupt handling mechanism, however, unless
and until such time as the execution is attempted of an instruction at an address associated
with the instruction fetch for which the Instruction Machine Check exception was asserted.
When the exception is presented, the ESR[MCI] bit will be set to indicated the type of excep-