AMD Elan SC520, User Manual, Page: 92 / 444

System Address Mapping
4-14 Élan™SC520 Microcontroller User’s Manual
The ÉlanSC520 microcontroller also allows the internal UARTs and the real-time clock
(RTC) to be disabled, for applications when an external device is preferred. This is controlled
by configuration register bits in the Address Decode Control (ADDDECCTL) register
(MMCR offset 80h). When these peripherals are disabled, the I/O cycle is forwarded
externally to the GP bus. This allows connection of external devices such as a standard
Super I/O chip.
Integrated PC/AT peripherals are not accessible by PCI bus masters.
4.3.4.5 GP Bus I/O Region
The PAR registers must be used to address external I/O devices on the GP bus. GP bus
addressing is implemented with byte granularity, to accommodate devices with very few
registers and very fragmented I/O maps that are typically found in PC/AT-compatible
systems.
When programming PAR registers for GP bus I/O space, it is best to configure the space
on doubleword boundaries. Note that when specifying unaligned byte regions for I/O
access, the software that accesses the regions must directly address the correct byte or
bytes. For example, if a PAR is programmed with an I/O region, and the start address is
xxx1h (i.e., byte #1), when the CPU performs a word or doubleword access starting at
xxx0h (i.e., byte #0), the entire doubleword access is redirected to the PCI bus (byte #1
will not be accessed on the GP bus as programmed). In this case, the byte requested
must
be directly accessed by the CPU at I/O address xxx1h.
This region is not accessible by PCI bus masters.
4.3.5 Configuration Information
4.3.5.1 Configuring ROM/Flash Space
There are three ROM address regions that can be defined in the ÉlanSC520 microcontroller,
but only the BOOTCS region is absolutely required for system boot up from reset. The
optional two regions, ROMCS1 and ROMCS2 are configured via PAR registers. BOOTCS
configuration is described in Chapter 3, “System Initialization”. See “Programmable
Address Region (PAR) Registers” on page 4-5 for details on PAR register programming.
4.3.5.2 Configuring SDRAM Address Space
SDRAM space is determined at boot time when the SDRAM controller’s configuration
registers are programmed and individual banks are enabled. A typical design can perform
an SDRAM sizing routine to determine the amount of memory installed in the system and
write the appropriate values to the configuration registers. For example, in a system that
contains 16 megabytes of SDRAM, initialization software defines the SDRAM address
region from 00000000–00FFFFFFh, and all accesses to this region are forwarded to the
SDRAM controller unless a PAR register has been programmed to overlay the region with
MMCR, ROM, PCI bus, or GP bus space.
Master GP Bus DMA Controller 00C0–00DEh
(even addresses only)
Floating Point Error Interrupt Clear 00F0h
UART 2 02F8–02FFh
UART 1 03F8–03FFh
Table 4-5 PC/AT Peripherals I/O Map (Continued)
Peripheral Core I/O Address Range